Proceedings of the 2021 International Symposium on Physical Design, 2021
The end of Moore's law has been proclaimed on many occasions and it's probably safe to sa... more The end of Moore's law has been proclaimed on many occasions and it's probably safe to say that we are now working in the post-Moore era. But no one is ready to slow down just yet. We can view Gordon Moore's observation on transistor densification as just one aspect of a longer-term underlying technological trend - the Law of Accelerating Returns articulated by Kurzweil. Arguably, companies became somewhat complacent in the Moore era, happy to settle for the gains brought by each new process node. Although we can expect scaling to continue, albeit at a slower pace, the end of Moore's Law delivers a stronger incentive to push other trends harder. Some exciting new technologies are now emerging such as multi-chip 3D integration and the introduction of new technologies such as storage-class memory and silicon photonics. Moreover, we are also entering a golden age of computer architecture innovation. One of the key drivers is the pursuit of domain-specific architectures as proclaimed by Turing award winners John Hennessy and David Patterson. A good example is the Xilinx's AI Engine, one of the important features of the Versal? ACAP (adaptive compute acceleration platform). Today, the explosion of AI workloads is one of the most powerful drivers shifting our attention to find faster ways of moving data into, across, and out of accelerators. Features such as massive parallel processing elements, the use of domain specific accelerators, the dense interconnect between distributed on-chip memories and processing elements, are examples of the ways chip makers are looking beyond scaling to achieve next-generation performance gains.
Modern FPGA platforms have capabilities that are well suited to assume a central role in the impl... more Modern FPGA platforms have capabilities that are well suited to assume a central role in the implementation of complex embedded systems. Today the design flow for FPGA has been largely characterized by a hardware centric approach. We will argue that there are many additional opportunities for mapping complex applications to these FPGA platforms. The requirement is the exposure of the high computational efficiency of FPGAs matched by high bandwidth concurrent memory access and rich on-chip interconnectivity, combined with complete programmability. These requirements make FPGAs well suited for efficient implementation of signal processing, packet processing and high performance computing applications. We will discuss different domain specific programming environments that rely on flexible and soft template architectures, represented by API' s that match the characteristics of a specific application domain. Next, system design flows compile high level programming constructs on thes...
2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017
Smart Systems create new challenges for semiconductor components that need to provide, at one han... more Smart Systems create new challenges for semiconductor components that need to provide, at one hand, the ease of software programmability and, on the other hand, the capability of hardware efficiency. This dichotomy is driven by, on the one hand, the need for a software stack that supports flexibility, scalability, fast development cycles and, on the other hand, the need for hardware optimization to support performance, efficiency and cost. In this talk, we will discuss the technical trends in major market segments such as datacenters, 5G wireless infrastructure and software defined networking and the resulting requirements for semiconductor platforms, both from hardware and software perspective. To provide an answer to these challenges, it will be demonstrated on how FPGA technology is evolving from a programmable hardware solution catering to ASIC refugees towards an All Programmable architecture empowering system and software engineers.
2010 International Conference on Field-Programmable Technology, 2010
Modern FPGA platforms have capabilities that are well suited to assume a more central role in the... more Modern FPGA platforms have capabilities that are well suited to assume a more central role in the implementation of complex embedded processing systems. The aggressive adoption of Moore's Law and the application of emerging 3D stacked silicon interconnect technology have resulted in the growth of FPGA capacity that outperforms Moore's Law.
High-Level Synthesis for Real-Time Digital Signal Processing, 1993
In the previous chapter, we have already indicated that the expansion of silage control functions... more In the previous chapter, we have already indicated that the expansion of silage control functions requires the generation of control structures. In this chapter, the generation of the control structures for implementation in a multi-branch controller with a single thread of control is explained. More in particular, we will consecutively treat the following topics: the conversion of selection multiplexers into blocks of conditionally executed register transfers the implementation of code repetition in a register-transfer description alternative ways to exploit function hierarchy the conversion of multi-rate silage descriptions into behaviourally equivalent single-rate descriptions. The discussion on the scheduling of the register transfers into a sequence of operations, is contained in chapter 6.
Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05, 2005
Abstract Electronic system-level (ESL) design automation has been identified by Dataquest as the ... more Abstract Electronic system-level (ESL) design automation has been identified by Dataquest as the next productivity boost for the semiconductor industry. We have put together a distinguished panel of experts to discuss if we are ready for system-level synthesis.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)
Abstract Wavelet-based image compression has been adopted in merging standards such as MPEG-4 [l]... more Abstract Wavelet-based image compression has been adopted in merging standards such as MPEG-4 [l] and JPEG2000 [2]. An embedded zero tree (EZT) coding scheme enables the compression and the quantization of the wavelet coefficients. This paper presents the OZONE chip, a ...
Proceedings of the 2021 International Symposium on Physical Design, 2021
The end of Moore's law has been proclaimed on many occasions and it's probably safe to sa... more The end of Moore's law has been proclaimed on many occasions and it's probably safe to say that we are now working in the post-Moore era. But no one is ready to slow down just yet. We can view Gordon Moore's observation on transistor densification as just one aspect of a longer-term underlying technological trend - the Law of Accelerating Returns articulated by Kurzweil. Arguably, companies became somewhat complacent in the Moore era, happy to settle for the gains brought by each new process node. Although we can expect scaling to continue, albeit at a slower pace, the end of Moore's Law delivers a stronger incentive to push other trends harder. Some exciting new technologies are now emerging such as multi-chip 3D integration and the introduction of new technologies such as storage-class memory and silicon photonics. Moreover, we are also entering a golden age of computer architecture innovation. One of the key drivers is the pursuit of domain-specific architectures as proclaimed by Turing award winners John Hennessy and David Patterson. A good example is the Xilinx's AI Engine, one of the important features of the Versal? ACAP (adaptive compute acceleration platform). Today, the explosion of AI workloads is one of the most powerful drivers shifting our attention to find faster ways of moving data into, across, and out of accelerators. Features such as massive parallel processing elements, the use of domain specific accelerators, the dense interconnect between distributed on-chip memories and processing elements, are examples of the ways chip makers are looking beyond scaling to achieve next-generation performance gains.
Modern FPGA platforms have capabilities that are well suited to assume a central role in the impl... more Modern FPGA platforms have capabilities that are well suited to assume a central role in the implementation of complex embedded systems. Today the design flow for FPGA has been largely characterized by a hardware centric approach. We will argue that there are many additional opportunities for mapping complex applications to these FPGA platforms. The requirement is the exposure of the high computational efficiency of FPGAs matched by high bandwidth concurrent memory access and rich on-chip interconnectivity, combined with complete programmability. These requirements make FPGAs well suited for efficient implementation of signal processing, packet processing and high performance computing applications. We will discuss different domain specific programming environments that rely on flexible and soft template architectures, represented by API' s that match the characteristics of a specific application domain. Next, system design flows compile high level programming constructs on thes...
2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017
Smart Systems create new challenges for semiconductor components that need to provide, at one han... more Smart Systems create new challenges for semiconductor components that need to provide, at one hand, the ease of software programmability and, on the other hand, the capability of hardware efficiency. This dichotomy is driven by, on the one hand, the need for a software stack that supports flexibility, scalability, fast development cycles and, on the other hand, the need for hardware optimization to support performance, efficiency and cost. In this talk, we will discuss the technical trends in major market segments such as datacenters, 5G wireless infrastructure and software defined networking and the resulting requirements for semiconductor platforms, both from hardware and software perspective. To provide an answer to these challenges, it will be demonstrated on how FPGA technology is evolving from a programmable hardware solution catering to ASIC refugees towards an All Programmable architecture empowering system and software engineers.
2010 International Conference on Field-Programmable Technology, 2010
Modern FPGA platforms have capabilities that are well suited to assume a more central role in the... more Modern FPGA platforms have capabilities that are well suited to assume a more central role in the implementation of complex embedded processing systems. The aggressive adoption of Moore's Law and the application of emerging 3D stacked silicon interconnect technology have resulted in the growth of FPGA capacity that outperforms Moore's Law.
High-Level Synthesis for Real-Time Digital Signal Processing, 1993
In the previous chapter, we have already indicated that the expansion of silage control functions... more In the previous chapter, we have already indicated that the expansion of silage control functions requires the generation of control structures. In this chapter, the generation of the control structures for implementation in a multi-branch controller with a single thread of control is explained. More in particular, we will consecutively treat the following topics: the conversion of selection multiplexers into blocks of conditionally executed register transfers the implementation of code repetition in a register-transfer description alternative ways to exploit function hierarchy the conversion of multi-rate silage descriptions into behaviourally equivalent single-rate descriptions. The discussion on the scheduling of the register transfers into a sequence of operations, is contained in chapter 6.
Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05, 2005
Abstract Electronic system-level (ESL) design automation has been identified by Dataquest as the ... more Abstract Electronic system-level (ESL) design automation has been identified by Dataquest as the next productivity boost for the semiconductor industry. We have put together a distinguished panel of experts to discuss if we are ready for system-level synthesis.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)
Abstract Wavelet-based image compression has been adopted in merging standards such as MPEG-4 [l]... more Abstract Wavelet-based image compression has been adopted in merging standards such as MPEG-4 [l] and JPEG2000 [2]. An embedded zero tree (EZT) coding scheme enables the compression and the quantization of the wavelet coefficients. This paper presents the OZONE chip, a ...
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