SDRs

This work grew out of didactic experience in architecture classes at the universities of Florence and Parma. The comprehension of geometric schemes in regular organic objects formed the basis of teaching drawing and scientific representation, such as formal architectural synthesis. This exercise may offer also a valid starting point to help students approach mathematics, and help them to imagine and plan the increasingly complex surfaces of late contemporary architecture.
Architecture origin is abscribed to Natur imitation, offering in its objects living models for structural, formal and aesthetic problems. Relationship between natural and artificial architectures trought geometry controlled parts composition and/or forms growth, underlines the concreteness of this classical myth.
Indeed observations of Natur’s patterns and formal phenomenous –on which classic thought and western science are based – offers solution to several project requirements, such as the serch of albertian concinnitas, finding satisfation in the composition armony components, specificable by forms and numbers (geometry and aritmetic).
Imitating organic forms and structures, architecture explains its strong relationship with primary geometry elements: numeric sequences, contolled by neat laws, characterise either building of creation or design.
Formal architectural archetypes, in static structures such as in surfaces patterns, are based on simple geometric scheme, easily connected with naturals models:
- modular aggregation (grid patterns)
- unity division (circle and polygons)
- continuous growth (spirals).
In this way, the references of Geometryare the first project means to concretise Idea to Design. They are able to fulfil several architecture requirement, such as Vitruvio’s concept of firmitas, utilitas, venustas.
Comparing wonderful variety of Nature’s objects with their built imitation, we find confirmation and new project stimulus.

References

Villard de Honnercourt, Disegni, Jaka Book, Milano, 1988.
Ian Stewart, What shape is a snowflake?, Weidenfeld & Nicolson, London, 2001.
Luca Pacioli, De divina proportione, Venezia, 1494.
Gottfried Semper, Der Stil, München, 1860-63.
Ernst Gömbrich, The sense of order, 1979.
Paolo Portoghesi, Natura e Architettura, Fabbri Editori, Milano, 1993.
D’Arcy W. Thomson, On Growth and Form, Abridged Edition, Cambridge, 1961.
Mario Livio, The golden ratio, Broadway, 2002.
M.C. Escher, His life and concrete graphic work, Abradale, New York, 1982.

Software defined radio (SDR) technology enables implementation of wireless devices that support multiple air-interfaces and modulation formats, which is very important if consider proliferation of wireless standards. To enable such functionality SDR is using reconfigurable hardware platform such as Field Programmable Gate Array (FPGA). In this paper, we present design procedure and implementation result of SDR based QPSK modulator on Altera Cyclone IV FPGA. For design and implementation of QPSK modulator we used Altera DSP Builder Tool combined with Matlab/Simulink, Modelsim and Quartus II design tools. As reconfigurable hardware platform we used Altera DE2-115 development and education board with AD/DA daughter card. Software and Hardware-in-the-loop (HIL) simulation was conducted before hardware implementation and verification of designed system. This method of design makes implementation of SDR based modulators simpler ad faster.

Security in every aspect is highly desirable may be at home or at office. Automated system specially designed to safeguard personal belonging, country’s secret, protection of secret research data, simple university building or a personal car, have been designed using various techniques of computing world both, software and hardware.
This paper tries to implement hardware based approach of designing security system. In this project FPGA based security system is designed capable of unlocking the door once the correct code is entered from DE2 board. Finally the output of overall system is evaluated based on the display on LCD present on De2 board of Altera Company.

The premise of this project is to provide a proof of
concept of Alamouti’s remarkably celebrated 2x1 transmit
diversity scheme with the aid of Software Defined Radios. We
aim at producing the same results as Alamouti, in an
environment that behaves as a frequency selective and slow
fading channel. The software-defined radios provide a
remote RF front-end to conduct this experiment however; the
real encoding and combining are done through Simulink
natively on external host machines

To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used layer 2 protocols. HDLC supports both full-duplex and half-duplex data transfer. In addition, it offers error control and flow control. Using a modified MT8952B controller design, the current research presents a new method for implementing an ultra high bit rate HDLC Controller that is compatible with ST-BUS format using Xilinx Virtex FPGA as the target technology using VHDL for implementation. The HDLC Transceiver is used to transmit and receive the HDLC frames. Implementing the HDLC protocol transceiver in FPGA offers the flexibility, upgradeability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.

Traffic Congestion is one of the severe problems in heavily populated countries like Bangladesh where Automated Traffic Control System needs to be implemented. An FPGA-based Semi-automated system is introduced in this paper including a completely new feature “Safe State” to avoid sudden unwanted collision. Here we used sequential encoding which has made the program much simpler and so that easy to control and modify. The experimental result showed the automated change in traffic lights according to the specified timing sequences which would be able to conduct maximum possible transitions of vehicles occur at different directions simultaneously without facing any accident.

Software defined radio (SDR) technology enables implementation of wireless devices that support multiple air-interfaces and modulation formats, which is very important if consider proliferation of wireless standards. To enable such functionality SDR is using reconfigurable hardware platform such as Field Programmable Gate Array (FPGA). In this paper, we present design procedure and implementation result of SDR based QPSK modulator on Altera Cyclone IV FPGA. For design and implementation of QPSK modulator we used Altera DSP Builder Tool combined with Matlab/Simulink, Modelsim and Quartus II design tools. As reconfigurable hardware platform we used Altera DE2-115 development and education board with AD/DA daughter card. Software and Hardware-in-the-loop (HIL) simulation was conducted before hardware implementation and verification of designed system. This method of design makes implementation of SDR based modulators simpler ad faster.

In the past decade, with an increased focus on core competencies, support functions and basic engineering designs have been increasingly outsourced. To this day, however, success is illusive to many outsourcers. This paper focuses on the potential of the Outsourcing and more on the capability of Bangladesh and how it can contribute to the International Engineering Outsourcing Arena. This research paper is done remembering the $55 billion outsourcing market of India, our neighboring country. We find that communication, the engagement of the appropriate resources, a mutual understanding of service delivery objective, and a cooperative, trust-building relationship can improve the chance of completing outsourcing initiatives successfully. The primary focus of the outsourcing Engineering Teams will be to support the engineering, design, and manufacturing and test needs of the manufacturing customers. Bangladesh can emerge as a very strong option In the International Engineering Outsourcing arena if proper steps are taken from now on. We put these findings into an outsourcing management framework for designs of PCB, FPGA, ASIC and even integration and synthesis of medium and small chips at a very low cost.

The investigation of neuron structures is an incredibly difficult and complex task that yields relatively low rewards in terms of
information from biological forms (either animals or tissue). The structures and connectivity of even the simplest invertebrates
are almost impossible to establish with standard laboratory techniques, and even when this is possible it is generally time
consuming, complex and expensive. Recent work has shown how a simplified behavioural approach to modelling neurons can allow
“virtual” experiments to be carried out that map the behaviour of a simulated structure onto a hypothetical biological one, with
correlation of behaviour rather than underlying connectivity. The problems with such approaches are numerous. The first is the
difficulty of simulating realistic aggregates efficiently, the second is making sense of the results and finally, it would be helpful to have
an implementation that could be synthesised to hardware for acceleration. In this paper we present a VHDL implementation of Neuron models that allow large aggregates to be
simulated. The models are demonstrated using a system level VHDL and VHDL-AMS model of the C. Elegans locomotory system.

VHDL models for neural networks for automatic test generation of gate level circuits are presented in this paper. A program converts a gate netlist to its equivalent neural model. A good circuit and faulty bad circuits will be generated. A VHDL test bench has been developed to apply the faults to the neural network bad circuit model, and report tests that are generated for each injected fault.

Emergent aquatic weeds present in the monocropped fresh water wetland area of Bangladesh create a hazard in land preparation by developing dense stands. A field experiment was conducted at the farmers’ field of two villages namely Mahilara and Kashemabad under Gournadi Upazila of Barisal district, Bangladesh during October 2012 to evaluate the efficacy of Gramoxone 20SL (Paraquat) in controlling emergent aquatic weeds and to find out an appropriate dose of this herbicide. Three doses of Gramoxone 20SL at 1.96 l·ha-1, 2.00 l·ha-1 and 2.04 l·ha-1 were tried with an untreated control. All treatments were laid out in a randomized complete block design and replicated thrice. There were 8 different emergent weed species infesting the field among which the most dominant weed species were Eichhornia crassipes, Pistia stratiotes, Enhydra fluctuans, Monochoria vaginalis, Echinochloa crus-galli. The results revealed that, weed control efficiency was significantly affected by different herbicidal treatments. The treatments, Gramoxone 20SL at 2.00 l·ha-1 and 2.04 l·ha-1 were controlled in all the emergent aquatic weeds more than 85% infesting both the sites. Application of non-selective herbicide Gramoxone 20SL at 2.00 l·ha-1 prior to land preparation was most effective to suppress weed dry masses in both the site resulting reduced land preparation cost up to 78.93% as compared to manual weed control.

Este art'iculo presenta un enfoque general para manejar los eventos de duraci'on breve en la sem'antica de los lenguajes de programaci'on de tiempo real, usando como ejemplo el lenguaje de descripci'on hardware VHDL, est'andar del IEEE.  Introducimos infinitesimales en la l'inea del tiempo para modelar dichos eventos. Demostramos que esto no afecta a la sem'antica que modela el comportamiento en tiempo apreciable.

This paper describes a Sandbridge Sandblaster system implementation including both hardware and software elements for a WiMAX 802.16e system. The system is implemented on the fully functional multithreaded Sandblaster multiprocessor SB3010 SoC chip. The entire communication protocol, physical layer and MAC, has been implemented in software using pure ANSI C programming language and it executes in real time. In this paper, we also present a radio propagation analysis specific to the Samos island at the workshop location, and the DSP execution performance.

This work presents a proposal and implementation of a reconfigurable parallel architecture, using Genetic Algorithms and applied to synthesis of combinational digital circuits. This reconfigurable parallel architecture uses concepts of computer architecture and parallel ...

The paper presents new approach to designing high efficient adaptive transmitting units (TU) for the sensor nodes of wireless sensor nets (WSN). Particularity of the considered TU is lack of digitizing and coding units. The signals formed by the sensors are transmitted to the base station (BS) using pulse-amplitude modulator adaptively adjusted during the samples transmission. The BS computes estimates of the origin signal, as well as the adjusting controls transmitted to TU through the feedback channel. Transition to the analogue transmission in the channel “node-BS” simplifies the construction of TU and enables development of analytical methods permitting to design optimal TU capable to transmit the signals to BS with minimal MSE and bit-rate equal to the capacity of the channel. The signals emitted by optimal TU have the form of realizations of white Gaussian noise that increases information security of data-transmission. The results of research enable transition to the practical design of low energy and low cost optimal TU which ensure “ideal” power-bandwidth trade off, i.e. work at the Shannon boundary.

... 305-316, May 1996. [7] C. Chakrabarti and M. Vishwanath, "Architectures for Wavelet Transforms: A Syrvey", Journal of VLSI Signal Processing, Kulwer, vol.lO, pp. ... 3-48, 2002. [11] Cyril PrsannaRaj and Citti babu, Pipelined OCT for image compression, SASTech Journal, Vol. ...

In this paper we are proposing a new concept in MAC layer protocol design for Cognitive radio by combining information held by physical layer and MAC layer with analytical engine based on knowledge based reasoning approach. In the proposed system a cross layer information regarding signal to interference and noise ratio (SINR) and received power are analyzed with help of knowledge based reasoning system to determine minimum power to transmit and size of contention window, to minimize backoff, collision, save power and drop packets. The performance analysis of the proposed protocol indicates improvement in power saving, lowering backoff and significant decrease in number of drop packets. The simulation environment was implement using OMNET++ discrete simulation tool with Mobilty framework and MiXiM simulation library.