FDSOI technology has been proposed as an alternative device scaling path which offers benefits of... more FDSOI technology has been proposed as an alternative device scaling path which offers benefits of tunable, superior electrostatics transistor while maintaining simplicity of planar integration. New device type and integration elements brought up challenges in device and process characterization and monitoring across the whole lifecycle of the technology. This paper presents successful application of fast cycle-time electrical characterization to ramp FDSOI technology to mass production.
Manufacturing an integrated circuit comprising an embodiment of metallization levels within isola... more Manufacturing an integrated circuit comprising an embodiment of metallization levels within isolation regions comprising a first material having a first dielectric constant, and a realization of at least one metal capacitor - insulator - metal comprising a metal reinforcements forming in at least one metallization level; the realization of the capacitor includes a local replacement of the first material (4) located between the metal fittings by at least a second material (8) having a second dielectric constant greater than the first dielectric constant.
An integrated circuit comprising at least one capacitor 6 formed on a layer 1 provided with at le... more An integrated circuit comprising at least one capacitor 6 formed on a layer 1 provided with at least one trench 2, said capacitor 6, having a dielectric layer 4 between two electrodes 3.5, matching the shape of the trench 2, the capacitor 6 leaving a portion 2d of the trench 2 and in that a material 7,8 capable of absorbing the stresses associated with movement of the trench walls is disposed in said portion 2d of the trench 2.
This paper summarizes the electromigration properties of thick copper lines embedded in BCB in BI... more This paper summarizes the electromigration properties of thick copper lines embedded in BCB in BICMOS technologies. It is shown that activation energy in the Cu/BCB architecture is quite low, and copper migration might preferentially occur at Cu/barrier and/or Cu/BCB interfaces. The adhesion of copper to barrier and copper to BCB or Si3N4 capping layers is determined and optimized. The increase
Post Si(C)N hillocks are characterized on Cu interconnects networks. Each network is compounded b... more Post Si(C)N hillocks are characterized on Cu interconnects networks. Each network is compounded by standard damascene process electroplated Cu lines with given width and local line density. AFM results show that total volume per area of post Si(C)N hillocks both on narrow and large lines increases linearly with local Cu line density. Two trends of hillocks nucleation and growth are
2007 IEEE International Conference on Microelectronic Test Structures, 2007
In this contribution we investigate the matching properties of modern high-k metal-insulator-meta... more In this contribution we investigate the matching properties of modern high-k metal-insulator-metal (MIM) capacitors. In particular, we derive a compact physics-based model in order to explain the observed geometry dependence of mismatch. This model is successfully applied to MIM devices processed with Ta2O5 and AI2O3 as dielectrics.
2006 European Solid-State Device Research Conference, 2006
Emmanuel Defaÿ, David Wolozan, Pierre Garrec, Bernard André, Laurent Ulmer, Marc Aïd CEA-LETI 380... more Emmanuel Defaÿ, David Wolozan, Pierre Garrec, Bernard André, Laurent Ulmer, Marc Aïd CEA-LETI 38054 Grenoble - France edefay@cea.fr ... Jean-Pierre Blanc, Emmanuelle Serret, Philippe Delpech, Jean-Christophe Giraudin, Julie Guillan, Denis Pellissier, ...
FDSOI technology has been proposed as an alternative device scaling path which offers benefits of... more FDSOI technology has been proposed as an alternative device scaling path which offers benefits of tunable, superior electrostatics transistor while maintaining simplicity of planar integration. New device type and integration elements brought up challenges in device and process characterization and monitoring across the whole lifecycle of the technology. This paper presents successful application of fast cycle-time electrical characterization to ramp FDSOI technology to mass production.
Manufacturing an integrated circuit comprising an embodiment of metallization levels within isola... more Manufacturing an integrated circuit comprising an embodiment of metallization levels within isolation regions comprising a first material having a first dielectric constant, and a realization of at least one metal capacitor - insulator - metal comprising a metal reinforcements forming in at least one metallization level; the realization of the capacitor includes a local replacement of the first material (4) located between the metal fittings by at least a second material (8) having a second dielectric constant greater than the first dielectric constant.
An integrated circuit comprising at least one capacitor 6 formed on a layer 1 provided with at le... more An integrated circuit comprising at least one capacitor 6 formed on a layer 1 provided with at least one trench 2, said capacitor 6, having a dielectric layer 4 between two electrodes 3.5, matching the shape of the trench 2, the capacitor 6 leaving a portion 2d of the trench 2 and in that a material 7,8 capable of absorbing the stresses associated with movement of the trench walls is disposed in said portion 2d of the trench 2.
This paper summarizes the electromigration properties of thick copper lines embedded in BCB in BI... more This paper summarizes the electromigration properties of thick copper lines embedded in BCB in BICMOS technologies. It is shown that activation energy in the Cu/BCB architecture is quite low, and copper migration might preferentially occur at Cu/barrier and/or Cu/BCB interfaces. The adhesion of copper to barrier and copper to BCB or Si3N4 capping layers is determined and optimized. The increase
Post Si(C)N hillocks are characterized on Cu interconnects networks. Each network is compounded b... more Post Si(C)N hillocks are characterized on Cu interconnects networks. Each network is compounded by standard damascene process electroplated Cu lines with given width and local line density. AFM results show that total volume per area of post Si(C)N hillocks both on narrow and large lines increases linearly with local Cu line density. Two trends of hillocks nucleation and growth are
2007 IEEE International Conference on Microelectronic Test Structures, 2007
In this contribution we investigate the matching properties of modern high-k metal-insulator-meta... more In this contribution we investigate the matching properties of modern high-k metal-insulator-metal (MIM) capacitors. In particular, we derive a compact physics-based model in order to explain the observed geometry dependence of mismatch. This model is successfully applied to MIM devices processed with Ta2O5 and AI2O3 as dielectrics.
2006 European Solid-State Device Research Conference, 2006
Emmanuel Defaÿ, David Wolozan, Pierre Garrec, Bernard André, Laurent Ulmer, Marc Aïd CEA-LETI 380... more Emmanuel Defaÿ, David Wolozan, Pierre Garrec, Bernard André, Laurent Ulmer, Marc Aïd CEA-LETI 38054 Grenoble - France edefay@cea.fr ... Jean-Pierre Blanc, Emmanuelle Serret, Philippe Delpech, Jean-Christophe Giraudin, Julie Guillan, Denis Pellissier, ...
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