Anomalous transconductance with nonmonotonic back-gate bias dependence observed in the fully depl... more Anomalous transconductance with nonmonotonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed. It is found that the anomalous transconductance is attributed to the domination of the back-channel charge in the total channel charge. This behavior is modeled with a novel two-mobility model, which separates the mobility of the front and back channels. These two mobilities are physically related by a charge-based weighting function. The proposed model is incorporated into BSIM-IMG and is in good agreement with the experimental and simulated data of FDSOI MOSFETs for various front-gate oxides, body thicknesses, and gate lengths.
We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest ... more We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility.
We report an experimental PFET with transconductance of 1800uS/um and 420GHz fT, which to the bes... more We report an experimental PFET with transconductance of 1800uS/um and 420GHz fT, which to the best of our knowledge is the highest values reported for a PFET. The technology is fully depleted silicon on insulator (FDSOI) with the PFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate lengths (22nm) in addition to the SiGe channel for high mobility and an aggressive effective channel length.
2007 International Workshop on Physics of Semiconductor Devices, 2007
In order to design integrated circuits which can be manufactured with high yield the variations w... more In order to design integrated circuits which can be manufactured with high yield the variations which can occur during manufacturing must be included with the compact models. The manufacturing variations comprise a complex correlated set of statistical distributions. This paper presents some of the current options and challenges in modeling variation. Improving the prediction of statistical circuit behavior will require
A simple and effective compact model methodology that predicts teh history effect in silicon-on-i... more A simple and effective compact model methodology that predicts teh history effect in silicon-on-insulator (SOI) is discussed. In this study we employ three physical parameters to modify the body-potentials of SOI FETs in an inverter during switching. These parameters are very challenging to measure accurately for sub 100nm device, year are very highly correlated with the history effect. This methodology provides an effective means of adjusting the history effects without significantly alteration of the DC model.
Anomalous transconductance with nonmonotonic back-gate bias dependence observed in the fully depl... more Anomalous transconductance with nonmonotonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed. It is found that the anomalous transconductance is attributed to the domination of the back-channel charge in the total channel charge. This behavior is modeled with a novel two-mobility model, which separates the mobility of the front and back channels. These two mobilities are physically related by a charge-based weighting function. The proposed model is incorporated into BSIM-IMG and is in good agreement with the experimental and simulated data of FDSOI MOSFETs for various front-gate oxides, body thicknesses, and gate lengths.
We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest ... more We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility.
We report an experimental PFET with transconductance of 1800uS/um and 420GHz fT, which to the bes... more We report an experimental PFET with transconductance of 1800uS/um and 420GHz fT, which to the best of our knowledge is the highest values reported for a PFET. The technology is fully depleted silicon on insulator (FDSOI) with the PFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate lengths (22nm) in addition to the SiGe channel for high mobility and an aggressive effective channel length.
2007 International Workshop on Physics of Semiconductor Devices, 2007
In order to design integrated circuits which can be manufactured with high yield the variations w... more In order to design integrated circuits which can be manufactured with high yield the variations which can occur during manufacturing must be included with the compact models. The manufacturing variations comprise a complex correlated set of statistical distributions. This paper presents some of the current options and challenges in modeling variation. Improving the prediction of statistical circuit behavior will require
A simple and effective compact model methodology that predicts teh history effect in silicon-on-i... more A simple and effective compact model methodology that predicts teh history effect in silicon-on-insulator (SOI) is discussed. In this study we employ three physical parameters to modify the body-potentials of SOI FETs in an inverter during switching. These parameters are very challenging to measure accurately for sub 100nm device, year are very highly correlated with the history effect. This methodology provides an effective means of adjusting the history effects without significantly alteration of the DC model.
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Papers by Josef Watts