Dans le cadre de la filière par apprentissage Microélectronique et Télécoms (MT) de l’école d’ing... more Dans le cadre de la filière par apprentissage Microélectronique et Télécoms (MT) de l’école d’ingénieurs Phelma-Grenoble INP, les étudiants de seconde année effectuent un projet au sein du CIME Nanotech durant leur second semestre dont l’objectif est la conception d’un « digital baseband controler » pour la norme ZigBee. Ils sont ainsi confrontés à une situation très proche de celle qu’ils connaîtront en milieu industriel car la conception d’une puce nécessite, non seulement d’en imaginer les plans, mais aussi d’effectuer de très nombreuses vérifications garantissant la manufacturabilité du circuit intégré, étapes nécessaires avant d’envoyer un circuit en fabrication via le CMP (Circuits Multi-Projets). Ces vérifications, pourtant indispensables, sont rarement effectuées lors des apprentissages en école car ces étapes sont extrêmement chronophages et requièrent persévérance et ténacité. Enfin, l’organisation de l’équipe et la gestion des tâches aux quotidiens sont aussi des éléments...
2009 IEEE International Conference on Control Applications, 2009
ABSTRACT The design of integrated circuits, especially system-on-chips (SoC) is now constrained b... more ABSTRACT The design of integrated circuits, especially system-on-chips (SoC) is now constrained by many parameters such as speed, energy but also the robustness to process variability. Indeed, controlling the speed and the energy in a complex SoCs - which adopt the globally asynchronous locally synchronous (GALS) paradigm - require specific power supplies and clock generators as actuators and dedicated sensors. The problem faced by the designers is the non-uniform and non-predictable behaviour of such systems which embed several microprocessors and complex network-on-chips (NoC). In these conditions, the control laws are difficult to establish. Moreover, with the technology shrink, the control needs are increased. In order to reach an acceptable fabrication yield, the clock synchronisation - based on the assumption that the critical path is shorter than the clock period - is impracticable with large SoCs which are divided in multiple clock domains. This is why specific sensors are used to evaluate the fabrication process quality and the local environmental parameters (voltage, temperature) in each clock region in order to determine the appropriate clock frequency which does not violate the local timing constraint. All these systems are fed back and required well-suited control techniques able to manage process variability as well as energy or speed.
... Self Adaption in SoCs. H. Zakaria 1 , E. Yahya 1, 2 , L. Fesquet 1. (2011). Power management ... more ... Self Adaption in SoCs. H. Zakaria 1 , E. Yahya 1, 2 , L. Fesquet 1. (2011). Power management techniques; Controlling uncertainty and handling process variability; Data synchronization in GALS system; Conclusions; Glossary. ...
2020 18th IEEE International New Circuits and Systems Conference (NEWCAS), 2020
The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM... more The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM based receivers. In this framework, a HR-NPM architecture has been discussed based on the π-delayed driving signals. The harmonic rejection and the system complexity have been improved with this new architecture such that the Harmonic rejection achieved by this structure is the same of the conventional HR-2NPM and the system complexity has been reduced by half, where as the number of the gain stages and the switches has been reduced. In this context, a 5-path mixer is thus proposed. It allows rejecting up to the 8th harmonic with only 2 differential gain stages by appropriately implementing the switches whereas only the 6th harmonic would be rejected with conventional HR-8PM topologies having 3 amplifier stages. Our structure shows high resilience to clocks overlapping effects.
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
The fast evolving pace of electronic mobile devices have made mandatory to reduce power consumpti... more The fast evolving pace of electronic mobile devices have made mandatory to reduce power consumption without compromising the circuit performance or its robustness. Asynchronous circuits have demonstrated to be an excellent solution to help designing robust and energy-efficient circuits required for the Internet-of-Things and the mobile applications. Their local synchronization mechanisms, based on handshake protocols, make them perfectly suitable for exploiting dynamic power management techniques, such as Adaptive Body Biasing (ABB) in FD-SOI technologies. Indeed, the circuit activity is simply detected by using the already existing handshake signals, enabling the application of different ABB strategies with almost no modification to the original asynchronous circuit. As the synchronization mechanisms are local to small logic blocks, the ABB strategy is able to target from small to large body bias domains. In order to manage such a technique, an analog dedicated standard cell has been designed to body bias small regions. Depending on the body bias domain granularity, an appropriated number of these specific cells is inserted exactly as logic standard cells during the back-end operations. Additionally, the robustness of asynchronous circuits makes possible changing the transistor threshold voltage on-the-fly, a requirement for applying ABB schemes without complex power management issues.
2016 31st Symposium on Microelectronics Technology and Devices (SBMicro), 2016
The expected development of connected objects appears as a key factor of the future worldwide eco... more The expected development of connected objects appears as a key factor of the future worldwide economy. The field of microelectronics is primarily concerned by this evolution because the connected objects involve the microelectronics industry and related research. In addition, the spectrum of the application domains can be very wide and the multidisciplinary approach appears mandatory. In parallel, the evolution of the microelectronics towards a larger integration implies new designs, and new technologies that must be assimilated by the students. The main challenge, today, is to give to these students and future engineers, the methodology and the know-how that can insure an innovative approach, by changing the educational structures and the behavior of the professorial body, while in the same time, the education systems want to massively introduce numerical tools. As a result, the introduction of new practices and laboratory works becomes increasingly useful, more especially in microelectronics. Indeed, this is a way to give to the students the knowledge and the know-how with an innovative behavior. However, the practice on microelectronic platforms is very expensive and the sharing of this equipment between several institutions is necessary. The French national network, CNFM (National Coordination for Education in Microelectronics and nanotechnologies), which pilots the 12 national platforms, tries to answer to these needs and has set-up a policy deliberately focused on innovative practices on dedicated platforms. Several suggestions are given in order to improve the educational system and create a model which could be duplicated in many other countries.
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016
3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologi... more 3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologies dealing with process variability. Using SPICE models and Monte Carlo simulations we show a delay partioning method for stacked circuits to reduce frequency dispersion by 30%. We also compare how the process correlation between tiers influences the design corners.
This paper aims at identifying the critical parameters for intermediate back end of line (BEOL) i... more This paper aims at identifying the critical parameters for intermediate back end of line (BEOL) in 3DVLSI in order to benefit from higher circuit gain in performance. Thanks to circuit simulations in a 3D environment PDK, the capacitance is identified as the most critical parameter for IC performance of circuits using two intermetal levels. The critical wirelength upon which a gain in performance is obtained by the 3D stacking is evaluated as a function of BEOL flavor.
2015 IEEE International Conference on Microelectronics Systems Education (MSE), 2015
ABSTRACT The evolution of the fields of microelectronics and nanotechnologies has presently two m... more ABSTRACT The evolution of the fields of microelectronics and nanotechnologies has presently two main orientations: on one hand, the ultra large scale integration with FinFET or FDSOI technologies, and on the other hand, the multidisciplinary approach to insert the new devices in systems, mainly the communicating objects and the smart objects, in terms of applications. This evolution asks to the teachers to adapt the theoretical contents of the courses and to renew the practice in order to create new knowledge, new skills and new know-how. The French national network, CNFM (National Coordination for Education in Microelectronics and nanotechnologies) has deliberately introduced in its strategy the incitation to the multidisciplinary innovative projects in the microelectronics centers of this network. This paper deals with this strategy and gives several recent examples of the application of this strategy.
Dans le cadre de la filière par apprentissage Microélectronique et Télécoms (MT) de l’école d’ing... more Dans le cadre de la filière par apprentissage Microélectronique et Télécoms (MT) de l’école d’ingénieurs Phelma-Grenoble INP, les étudiants de seconde année effectuent un projet au sein du CIME Nanotech durant leur second semestre dont l’objectif est la conception d’un « digital baseband controler » pour la norme ZigBee. Ils sont ainsi confrontés à une situation très proche de celle qu’ils connaîtront en milieu industriel car la conception d’une puce nécessite, non seulement d’en imaginer les plans, mais aussi d’effectuer de très nombreuses vérifications garantissant la manufacturabilité du circuit intégré, étapes nécessaires avant d’envoyer un circuit en fabrication via le CMP (Circuits Multi-Projets). Ces vérifications, pourtant indispensables, sont rarement effectuées lors des apprentissages en école car ces étapes sont extrêmement chronophages et requièrent persévérance et ténacité. Enfin, l’organisation de l’équipe et la gestion des tâches aux quotidiens sont aussi des éléments...
2009 IEEE International Conference on Control Applications, 2009
ABSTRACT The design of integrated circuits, especially system-on-chips (SoC) is now constrained b... more ABSTRACT The design of integrated circuits, especially system-on-chips (SoC) is now constrained by many parameters such as speed, energy but also the robustness to process variability. Indeed, controlling the speed and the energy in a complex SoCs - which adopt the globally asynchronous locally synchronous (GALS) paradigm - require specific power supplies and clock generators as actuators and dedicated sensors. The problem faced by the designers is the non-uniform and non-predictable behaviour of such systems which embed several microprocessors and complex network-on-chips (NoC). In these conditions, the control laws are difficult to establish. Moreover, with the technology shrink, the control needs are increased. In order to reach an acceptable fabrication yield, the clock synchronisation - based on the assumption that the critical path is shorter than the clock period - is impracticable with large SoCs which are divided in multiple clock domains. This is why specific sensors are used to evaluate the fabrication process quality and the local environmental parameters (voltage, temperature) in each clock region in order to determine the appropriate clock frequency which does not violate the local timing constraint. All these systems are fed back and required well-suited control techniques able to manage process variability as well as energy or speed.
... Self Adaption in SoCs. H. Zakaria 1 , E. Yahya 1, 2 , L. Fesquet 1. (2011). Power management ... more ... Self Adaption in SoCs. H. Zakaria 1 , E. Yahya 1, 2 , L. Fesquet 1. (2011). Power management techniques; Controlling uncertainty and handling process variability; Data synchronization in GALS system; Conclusions; Glossary. ...
2020 18th IEEE International New Circuits and Systems Conference (NEWCAS), 2020
The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM... more The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM based receivers. In this framework, a HR-NPM architecture has been discussed based on the π-delayed driving signals. The harmonic rejection and the system complexity have been improved with this new architecture such that the Harmonic rejection achieved by this structure is the same of the conventional HR-2NPM and the system complexity has been reduced by half, where as the number of the gain stages and the switches has been reduced. In this context, a 5-path mixer is thus proposed. It allows rejecting up to the 8th harmonic with only 2 differential gain stages by appropriately implementing the switches whereas only the 6th harmonic would be rejected with conventional HR-8PM topologies having 3 amplifier stages. Our structure shows high resilience to clocks overlapping effects.
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
The fast evolving pace of electronic mobile devices have made mandatory to reduce power consumpti... more The fast evolving pace of electronic mobile devices have made mandatory to reduce power consumption without compromising the circuit performance or its robustness. Asynchronous circuits have demonstrated to be an excellent solution to help designing robust and energy-efficient circuits required for the Internet-of-Things and the mobile applications. Their local synchronization mechanisms, based on handshake protocols, make them perfectly suitable for exploiting dynamic power management techniques, such as Adaptive Body Biasing (ABB) in FD-SOI technologies. Indeed, the circuit activity is simply detected by using the already existing handshake signals, enabling the application of different ABB strategies with almost no modification to the original asynchronous circuit. As the synchronization mechanisms are local to small logic blocks, the ABB strategy is able to target from small to large body bias domains. In order to manage such a technique, an analog dedicated standard cell has been designed to body bias small regions. Depending on the body bias domain granularity, an appropriated number of these specific cells is inserted exactly as logic standard cells during the back-end operations. Additionally, the robustness of asynchronous circuits makes possible changing the transistor threshold voltage on-the-fly, a requirement for applying ABB schemes without complex power management issues.
2016 31st Symposium on Microelectronics Technology and Devices (SBMicro), 2016
The expected development of connected objects appears as a key factor of the future worldwide eco... more The expected development of connected objects appears as a key factor of the future worldwide economy. The field of microelectronics is primarily concerned by this evolution because the connected objects involve the microelectronics industry and related research. In addition, the spectrum of the application domains can be very wide and the multidisciplinary approach appears mandatory. In parallel, the evolution of the microelectronics towards a larger integration implies new designs, and new technologies that must be assimilated by the students. The main challenge, today, is to give to these students and future engineers, the methodology and the know-how that can insure an innovative approach, by changing the educational structures and the behavior of the professorial body, while in the same time, the education systems want to massively introduce numerical tools. As a result, the introduction of new practices and laboratory works becomes increasingly useful, more especially in microelectronics. Indeed, this is a way to give to the students the knowledge and the know-how with an innovative behavior. However, the practice on microelectronic platforms is very expensive and the sharing of this equipment between several institutions is necessary. The French national network, CNFM (National Coordination for Education in Microelectronics and nanotechnologies), which pilots the 12 national platforms, tries to answer to these needs and has set-up a policy deliberately focused on innovative practices on dedicated platforms. Several suggestions are given in order to improve the educational system and create a model which could be duplicated in many other countries.
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016
3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologi... more 3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologies dealing with process variability. Using SPICE models and Monte Carlo simulations we show a delay partioning method for stacked circuits to reduce frequency dispersion by 30%. We also compare how the process correlation between tiers influences the design corners.
This paper aims at identifying the critical parameters for intermediate back end of line (BEOL) i... more This paper aims at identifying the critical parameters for intermediate back end of line (BEOL) in 3DVLSI in order to benefit from higher circuit gain in performance. Thanks to circuit simulations in a 3D environment PDK, the capacitance is identified as the most critical parameter for IC performance of circuits using two intermetal levels. The critical wirelength upon which a gain in performance is obtained by the 3D stacking is evaluated as a function of BEOL flavor.
2015 IEEE International Conference on Microelectronics Systems Education (MSE), 2015
ABSTRACT The evolution of the fields of microelectronics and nanotechnologies has presently two m... more ABSTRACT The evolution of the fields of microelectronics and nanotechnologies has presently two main orientations: on one hand, the ultra large scale integration with FinFET or FDSOI technologies, and on the other hand, the multidisciplinary approach to insert the new devices in systems, mainly the communicating objects and the smart objects, in terms of applications. This evolution asks to the teachers to adapt the theoretical contents of the courses and to renew the practice in order to create new knowledge, new skills and new know-how. The French national network, CNFM (National Coordination for Education in Microelectronics and nanotechnologies) has deliberately introduced in its strategy the incitation to the multidisciplinary innovative projects in the microelectronics centers of this network. This paper deals with this strategy and gives several recent examples of the application of this strategy.
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Papers by L. Fesquet