Hatem Zakaria

Orthogonal frequency division multiplexing (OFDM) systems are very sensitive to the frequency synchronization errors in form of carrier frequency offset (CFO). CFO can lead to the Inter-Carrier interference (ICI) and also destroys the orthogonality between sub-carriers. Therefore, CFO plays a key role in Frequency synchronization. Basically for getting a good performance of OFDM, the CFO should be estimated and compensated. In this paper we investigate the algorithms for the CFO estimation in OFDM systems. Four types of estimators are investigated: cyclic prefix (CP) and Training Sequence based estimators in time domain in addition to Training Symbol based and pilot tone based estimators in frequency domain. Mean Square Error (MSE) is the comparison criteria used in studying the performance. Simulation results indicate the performance of the different estimators over both additive white Gaussian noise (AWGN) and four taps multipath fading channels. Keywords—Orthogonal frequency divi...

Several algorithms have been proposed to avoid the error floor region, such as the concatenation codes that requires high computational demands in addition to high complexity. This paper proposes a technique based on using cascaded BCH and convolutional codes that leads to better error correction performance. Moreover, an adaptive method based on sensing the channel's noise to determine the number of the parity bits that will be added to the used BCH that reduces the consumed bandwidth and the transmitted parity bits is presented. A further enhancement is fulfilled by using parallel processing branches, resulting in reducing the consumed time and speed up the performance. The results show that the proposed code presents a better performance. A high reduction in the number of cycles that will be used in the encoding and decoding compared with the classical method and finally a flexible parity bits method based on the signal-to-noise ratio of the channel that reduced the parity bi...

This paper presents an implementation of a 3-bit soft decision Viterbi decoder. It uses survivor path with parameters for wireless communication in an attempt to reduce the power, area, and cost. At the same time, it increases the speed. The circuit design supports a constraint length of seven and a code rate of 0.5. The convolution encoder and the 3-bit soft decision Viterbi decoder are implemented on Virtex-6 XC6VLX240T FPGA at 66 MHZ core frequency starter kit. Xilinx ISE12.1 series is used for simulation. The implemented design shows an area overhead reduction of 50% compared to Spartan 3E device. In a Virtex-6 the proposal achieved 2014 LUTs in compared with Spartan 3E solutions, 3155 LUTs are achievable compared with Virtex_5 solutions. In addition, Slice Registers occupied 1011 , while 3214 in Spartan 3E then 69% are achievable in Virtex 5, then Virtex 6 better than previous state-of theart solutions in terms of area, Higher data rates. Moreover, the implemented Viterbi decod...

Many Processor Systems-on-Chip (MPSoC) have become tremendously complex systems. They are more sensitive to variability with technology scaling, which complica tes the system design and impact the overall performance. Energy consumption is also of great interest for mobile platforms powe red by battery and power management techniques, mainly based on Dynamic Voltage and Frequency Scaling (DVFS) algorithms, become mandatory. A Globally Asynchronous Locally Synchronous (GALS) design alleviate such problems by having multiple clocks, each one being distributed on a small area of the chip (called island), whereas an Asynchronous Network-on-Chip (ANoC) allow to communicate between the different islands. A robust technique is proposed to deal with a GALS-ANoC architecture under process variability constraints using advanced automatic control methods. The approach relaxes the fabrication constraints and help to the yield enhancement. More over, energy savings are even better for the same p...

When transmitting the data in digital communication, it is well desired that the transmitting data bits should be as minimal as possible, so many techniques are used to compress the data. In this paper, a Lempel-Ziv algorithm for data compression was implemented through VHDL coding. One of the most lossless data compression algorithms commonly used is Lempel-Ziv. The work in this paper is devoted to improve the compression rate, space-saving, and utilization of the Lempel-Ziv algorithm using a systolic array approach. The developed design is validated with VHDL simulations using Xilinx ISE 14.5 and synthesized on Virtex-6 FPGA chip. The results show that our design is efficient in providing high compression rates and space-saving percentage as well as improved utilization. The Throughput is increased by 50% and the design area is decreased by more than 23% with a high compression ratio compared to comparable previous designs.

The design of complex systems-on-chip (SoCs) in the upcoming CMOS technologies has become increasingly challenging due to the high levels of integration, the excessive energy consumption and the increased process variability impact. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency domains and propose an efficient control algorithm for on-the-fly workload monitoring and management. This

Code Division Multiple Access (CDMA) is interference limited multiple access system. Because all users transmit on the same frequency, internal interference generated by the system is the most significant factor in determining system capacity and call quality. The transmit power for each user must be reduced to limit interference, however, the power should be enough to maintain the required signal energy per bit to noise power spectral density ratio (Eb/No) for a satisfactory call quality. Maximum capacity is achieved when Eb/No of every user is at the minimum level needed for the acceptable channel performance. As the mobile station (MS) moves around, the radio frequency (RF) environment continuously changes due to fast and slow fading, external interference, shadowing, and other factors. The aim of the dynamic power control is to limit transmitted power on both the links while maintaining link quality under all conditions. Additional advantages are longer mobile battery life and l...

ABSTRACT Continuous scaling of CMOS technology push circuit designs towards multi-core complex SoCs. Moreover, with the nanometric technologies, the integrated system performances after fabrication will not be fully predictable. Indeed, the process variations really become huge at the chip scale. Therefore the design of such complex SoCs in the nanoscale technologies is now constrained by many parameters such as the energy consumption and the robustness to process variability. This implies the need of efficient algorithms and built-in circuitry able to adapt the system behavior to the workload variations and, at the same time, to cope with the parameter variations which cannot be predicted or accurately modeled at design time. In this context, this thesis work addresses the design of GALS-based NoC architectures in the upcoming CMOS technologies. A novel methodology to dynamically control the speed of different voltage-frequency NoC islands according to the process variability impact on each domain is proposed. This control technique can improve the performances, the energy consumption, and the yield of future SoC architectures in a synergistic manner. The control methodology is based on the design of an asynchronous programmable self-timed ring where the controller takes into account the dynamic workload and the process variability effects. The controller especially considers the operating frequency limit which does not exceed the maximum locally allowed value for a given clock domain. With such an approach, it is no more required to separately guaranty the performance for each node. This drastically relaxes the fabrication constraints and helps the yield enhancement.

Message from Chairs .................................................................................................. vii Organizing Committee ................................................................................................ ... ... Programmable/Stoppable Oscillator Based on Self-Timed Rings ................................................................ 3 Eslam Yahya, ...