Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1997
This paper presents theory and practical implementation of a method for multi-level logic synthes... more This paper presents theory and practical implementation of a method for multi-level logic synthesis of speedindependent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but is technology independent. The proposed method performs both combinational (inserting new gates) and sequential (inserting new memory elements) decomposition of complex gates in a given standard cell library, while preserving original behaviour and speed-independence. The algorithm applies known efficient algebraic factorization techniques from combinational multi-level logic synthesis, but achieves also boolean simplification and sequential decomposition. The method allows sharing of decomposed logic.
Proceedings 1998 International Conference on Application of Concurrency to System Design, 1998
State coding conflict detection is a fundamental part of synthesis of asynchronous concurrent sys... more State coding conflict detection is a fundamental part of synthesis of asynchronous concurrent systems from their specifications as Signal Transition Graphs (STGs), which are a special kind of labelled Petri nets. The paper develops a method for identifying state coding conflicts in STGs that is intended to work within a new synthesis framework based on Petri net unfolding. The latter offers potential advantages due to a partial order representation of highly concurrent behaviour as opposed to the more traditional construction of a state graph, known to suffer from combinatorial explosion. We develop a necessary condition for coding conflicts to exist, by using an approximate state covering approach. Being computationally easy, yet conservative, such a solution may produce fake conflicts. A technique for refining the latter, with extra computational cost, is provided.
Functional and performance correctness of on-die communication fabrics is critical for the design... more Functional and performance correctness of on-die communication fabrics is critical for the design of modern computer systems. In this talk we will examine some challenges and open problems in functional verification communication fabrics and in their quality of service analysis and optimization. We will also review some progress that has been done in liveness verification of communication fabrics.
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), 2003
Synchronous languages such as Esterel, Lustre, Signal, and others were originally developed for s... more Synchronous languages such as Esterel, Lustre, Signal, and others were originally developed for safety-critical embedded software and compiled into C. They have recently been extended to hardware with new language features and compilers to RTL. Contrary to traditional HDL languages (Verilog, VHDL) and recent system-level languages (SystemC, System Verilog), they have well defined formal semantics, which facilitate bug avoidance using correct-by-construction compilation and verification techniques.
Proceedings of the 31st annual conference on Design automation conference - DAC '94, 1994
Determining the cycle time and a critical cycle is a fundamental problem in the analysis of concu... more Determining the cycle time and a critical cycle is a fundamental problem in the analysis of concurrent systems. We solve this problem using timing simulation of an underlying Signal Graph (an extension of Marked Graphs). For a Signal Graph with n vertices and m arcs our algorithm has the polynomial time complexity O(b 2 m), where b is the number of vertices with initially marked in . The algorithm has a clear semantic and a low descriptive complexity. We illustrate the use of the algorithm by applying it to performance analysis of asynchronous circuits.
Abstract. This paper suggests a way for Petri Net analysis by checking the ordering relations bet... more Abstract. This paper suggests a way for Petri Net analysis by checking the ordering relations between places and transitions. The method is based on un-folding the original net into an equivalent azyclic description. In an unfolding the ordering relations can be determined directly by ...
Springer Series in Advanced Microelectronics, 2002
ABSTRACT Publisher’s description: This book is devoted to logic synthesis and design techniques f... more ABSTRACT Publisher’s description: This book is devoted to logic synthesis and design techniques for asynchronous circuits. It uses the mathematical theory of Petri nets and asynchronous automata to develop practical algorithms implemented in a public domain CAD tool. Asynchronous circuits have so far been designed mostly by hand, and are thus much less common than their synchronous counterparts, which have enjoyed a high level of design automation since the mid-1970s. Asynchronous circuits, on the other hand, can be very useful to tackle clock distribution, modularity, power dissipation and electro-magnetic interference in digital integrated circuits. This book provides the foundation needed for CAD-assisted design of such circuits, and can also be used as the basis for a graduate course on logic design.
Springer Series in Advanced Microelectronics, 2002
This chapter tackles one of the main problems of asynchronous circuit design: that of decomposing... more This chapter tackles one of the main problems of asynchronous circuit design: that of decomposing a complex Boolean function into elementary gates from a given library. In the synchronous case this is traditionally solved as two sub-problems. During the technology-independent phase [7, 8, 122, 10] one applies the theorems of Boolean algebra, and in particular Boolean and algebraic division operations, to optimally decompose the logic with a technology-independent cost function (e.g. literals for area and levels for delay). The result of this phase is a netlist of “canonical” technology-independent basic gates (e.g. inverters and 2-input nand gates). During the technology-dependent phase one maps the decomposed logic to the gates that are available in the library [123, 124]. The cost function at this stage may include more precise area and delay information, possibly including the effect of capacitive load and wiring estimates derived from approximate placement. Throughout this chapter we will assume a good knowledge of combinational logic synthesis techniques, as described in the above references.
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995
This paper presents a method to synthesize labeled Petri nets from state-based models. Although s... more This paper presents a method to synthesize labeled Petri nets from state-based models. Although state-based models (such as Finite State Machines) are a powerful formalism to describe the behavior of sequential systems, they cannot explicitly express the notions of concurrency, causality and con ict. Petri nets can naturally capture these notions.
Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012), 2012
Page 1. Compositional Performance Verification of NoC Designs Daniel E. Holcomb UC Berkeley Alexa... more Page 1. Compositional Performance Verification of NoC Designs Daniel E. Holcomb UC Berkeley Alexander Gotmanov Intel Michael Kishinevsky Intel Sanjit A. Seshia UC Berkeley Abstract—We present a compositional approach ...
Proceedings European Design and Test Conference. ED & TC 97, 1997
This paper presents a solution to the problem of sequential multi-level logic synthesis of asynch... more This paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, e.g., the monotonous cover conditions. We describe an algorithm for the factorization of this circuit aimed at implementing it in a given standard cell library, while preserving speed-independence. The algorithm exploits known ecient factorization techniques from combinational multi-level logic synthesis, but achieves also boolean simplication. Experimental results show a signicant improvement in terms of number and complexity of solvable circuits with respect to existing methods.
1997 IEEE International Conference on Systems, Man, and Cybernetics. Computational Cybernetics and Simulation, 1997
Abstract An unfolding is a finite acyclic prefix of a Petri Net behavior, which preserves all ess... more Abstract An unfolding is a finite acyclic prefix of a Petri Net behavior, which preserves all essential properties of the original Petri net, in particular all reachable markings of the net. An unfolding allows onc to analyze partial orders between instances of places and events of the ...
Heating in the Alfve´n resonant regime has been demonstrated in the Phaedrus-T tokamak [Fusion Te... more Heating in the Alfve´n resonant regime has been demonstrated in the Phaedrus-T tokamak [Fusion Technol. 19, 1327 (1991)]. Electron heating during injection of radio-frequency (rf) power is indicated by a 30%–40% drop in loop voltage and modifications in sawtooth activity. Heating was observed at a frequency ωrf≊0.7Ωi on axis, using a two-strap fast wave antenna operated at 7 and 9.2
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013
ABSTRACT Power consumption has been one of the major design considerations for more than a decade... more ABSTRACT Power consumption has been one of the major design considerations for more than a decade [6]. Hence, energy efficient techniques have been widely studied to harness the processing power within available power and thermal budgets [3][4][10]. With the proliferation of smart mobile devices, the criticality of energy efficiency is multiplied. On one hand, increasing computational power as well as sensing, storage, and communication capabilities open up wide range of power-hungry application domains. On the other hand, the battery life rises as one of the major concerns of the end user [9]. Furthermore, these fanless devices are subject to tight surface, or skin, temperature constraints which limit the peak power consumption, since the skin temperature directly affects the user experience (UX). As a result, power management techniques crafted specifically for smart mobile devices become necessary. In this paper, we review three differentiating aspects for managing the power of smart mobile devices. More specifically, we emphasize the importance of platform view, user experience and platform level optimization.
Proceedings of the International Workshop on System Level Interconnect Prediction - SLIP '12, 2012
ABSTRACT Design of SoCs as well as general purpose client and server systems rely increasingly on... more ABSTRACT Design of SoCs as well as general purpose client and server systems rely increasingly on integrating available IP cores such as processing cores, accelerators and memory blocks to improve energy efficiency, reduce time to market and/or cost. As a result, the communication fabric, i.e. the glue logic between the modules and IP blocks, becomes a critical component with significant implications on system-level power, performance and area. At the same time, if not designed carefully, fabric design can adversely impact the design time and functional correctness due to its complex distributed nature. Therefore, tools and methodologies that are aware of physical constraints (area, wire congestion), design quality (power, performance) and correctness (freedom of deadlocks and livelocks) are needed for efficient design space exploration and fabric generation and design. This tutorial will overview design and optimization of communication fabrics by using examples from both the high performance CMP and SoC domains. Design methodology and outstanding challenges will be illustrated using the xPLORE framework.
Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1997
This paper presents theory and practical implementation of a method for multi-level logic synthes... more This paper presents theory and practical implementation of a method for multi-level logic synthesis of speedindependent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but is technology independent. The proposed method performs both combinational (inserting new gates) and sequential (inserting new memory elements) decomposition of complex gates in a given standard cell library, while preserving original behaviour and speed-independence. The algorithm applies known efficient algebraic factorization techniques from combinational multi-level logic synthesis, but achieves also boolean simplification and sequential decomposition. The method allows sharing of decomposed logic.
Proceedings 1998 International Conference on Application of Concurrency to System Design, 1998
State coding conflict detection is a fundamental part of synthesis of asynchronous concurrent sys... more State coding conflict detection is a fundamental part of synthesis of asynchronous concurrent systems from their specifications as Signal Transition Graphs (STGs), which are a special kind of labelled Petri nets. The paper develops a method for identifying state coding conflicts in STGs that is intended to work within a new synthesis framework based on Petri net unfolding. The latter offers potential advantages due to a partial order representation of highly concurrent behaviour as opposed to the more traditional construction of a state graph, known to suffer from combinatorial explosion. We develop a necessary condition for coding conflicts to exist, by using an approximate state covering approach. Being computationally easy, yet conservative, such a solution may produce fake conflicts. A technique for refining the latter, with extra computational cost, is provided.
Functional and performance correctness of on-die communication fabrics is critical for the design... more Functional and performance correctness of on-die communication fabrics is critical for the design of modern computer systems. In this talk we will examine some challenges and open problems in functional verification communication fabrics and in their quality of service analysis and optimization. We will also review some progress that has been done in liveness verification of communication fabrics.
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), 2003
Synchronous languages such as Esterel, Lustre, Signal, and others were originally developed for s... more Synchronous languages such as Esterel, Lustre, Signal, and others were originally developed for safety-critical embedded software and compiled into C. They have recently been extended to hardware with new language features and compilers to RTL. Contrary to traditional HDL languages (Verilog, VHDL) and recent system-level languages (SystemC, System Verilog), they have well defined formal semantics, which facilitate bug avoidance using correct-by-construction compilation and verification techniques.
Proceedings of the 31st annual conference on Design automation conference - DAC '94, 1994
Determining the cycle time and a critical cycle is a fundamental problem in the analysis of concu... more Determining the cycle time and a critical cycle is a fundamental problem in the analysis of concurrent systems. We solve this problem using timing simulation of an underlying Signal Graph (an extension of Marked Graphs). For a Signal Graph with n vertices and m arcs our algorithm has the polynomial time complexity O(b 2 m), where b is the number of vertices with initially marked in . The algorithm has a clear semantic and a low descriptive complexity. We illustrate the use of the algorithm by applying it to performance analysis of asynchronous circuits.
Abstract. This paper suggests a way for Petri Net analysis by checking the ordering relations bet... more Abstract. This paper suggests a way for Petri Net analysis by checking the ordering relations between places and transitions. The method is based on un-folding the original net into an equivalent azyclic description. In an unfolding the ordering relations can be determined directly by ...
Springer Series in Advanced Microelectronics, 2002
ABSTRACT Publisher’s description: This book is devoted to logic synthesis and design techniques f... more ABSTRACT Publisher’s description: This book is devoted to logic synthesis and design techniques for asynchronous circuits. It uses the mathematical theory of Petri nets and asynchronous automata to develop practical algorithms implemented in a public domain CAD tool. Asynchronous circuits have so far been designed mostly by hand, and are thus much less common than their synchronous counterparts, which have enjoyed a high level of design automation since the mid-1970s. Asynchronous circuits, on the other hand, can be very useful to tackle clock distribution, modularity, power dissipation and electro-magnetic interference in digital integrated circuits. This book provides the foundation needed for CAD-assisted design of such circuits, and can also be used as the basis for a graduate course on logic design.
Springer Series in Advanced Microelectronics, 2002
This chapter tackles one of the main problems of asynchronous circuit design: that of decomposing... more This chapter tackles one of the main problems of asynchronous circuit design: that of decomposing a complex Boolean function into elementary gates from a given library. In the synchronous case this is traditionally solved as two sub-problems. During the technology-independent phase [7, 8, 122, 10] one applies the theorems of Boolean algebra, and in particular Boolean and algebraic division operations, to optimally decompose the logic with a technology-independent cost function (e.g. literals for area and levels for delay). The result of this phase is a netlist of “canonical” technology-independent basic gates (e.g. inverters and 2-input nand gates). During the technology-dependent phase one maps the decomposed logic to the gates that are available in the library [123, 124]. The cost function at this stage may include more precise area and delay information, possibly including the effect of capacitive load and wiring estimates derived from approximate placement. Throughout this chapter we will assume a good knowledge of combinational logic synthesis techniques, as described in the above references.
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995
This paper presents a method to synthesize labeled Petri nets from state-based models. Although s... more This paper presents a method to synthesize labeled Petri nets from state-based models. Although state-based models (such as Finite State Machines) are a powerful formalism to describe the behavior of sequential systems, they cannot explicitly express the notions of concurrency, causality and con ict. Petri nets can naturally capture these notions.
Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012), 2012
Page 1. Compositional Performance Verification of NoC Designs Daniel E. Holcomb UC Berkeley Alexa... more Page 1. Compositional Performance Verification of NoC Designs Daniel E. Holcomb UC Berkeley Alexander Gotmanov Intel Michael Kishinevsky Intel Sanjit A. Seshia UC Berkeley Abstract—We present a compositional approach ...
Proceedings European Design and Test Conference. ED & TC 97, 1997
This paper presents a solution to the problem of sequential multi-level logic synthesis of asynch... more This paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, e.g., the monotonous cover conditions. We describe an algorithm for the factorization of this circuit aimed at implementing it in a given standard cell library, while preserving speed-independence. The algorithm exploits known ecient factorization techniques from combinational multi-level logic synthesis, but achieves also boolean simplication. Experimental results show a signicant improvement in terms of number and complexity of solvable circuits with respect to existing methods.
1997 IEEE International Conference on Systems, Man, and Cybernetics. Computational Cybernetics and Simulation, 1997
Abstract An unfolding is a finite acyclic prefix of a Petri Net behavior, which preserves all ess... more Abstract An unfolding is a finite acyclic prefix of a Petri Net behavior, which preserves all essential properties of the original Petri net, in particular all reachable markings of the net. An unfolding allows onc to analyze partial orders between instances of places and events of the ...
Heating in the Alfve´n resonant regime has been demonstrated in the Phaedrus-T tokamak [Fusion Te... more Heating in the Alfve´n resonant regime has been demonstrated in the Phaedrus-T tokamak [Fusion Technol. 19, 1327 (1991)]. Electron heating during injection of radio-frequency (rf) power is indicated by a 30%–40% drop in loop voltage and modifications in sawtooth activity. Heating was observed at a frequency ωrf≊0.7Ωi on axis, using a two-strap fast wave antenna operated at 7 and 9.2
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013
ABSTRACT Power consumption has been one of the major design considerations for more than a decade... more ABSTRACT Power consumption has been one of the major design considerations for more than a decade [6]. Hence, energy efficient techniques have been widely studied to harness the processing power within available power and thermal budgets [3][4][10]. With the proliferation of smart mobile devices, the criticality of energy efficiency is multiplied. On one hand, increasing computational power as well as sensing, storage, and communication capabilities open up wide range of power-hungry application domains. On the other hand, the battery life rises as one of the major concerns of the end user [9]. Furthermore, these fanless devices are subject to tight surface, or skin, temperature constraints which limit the peak power consumption, since the skin temperature directly affects the user experience (UX). As a result, power management techniques crafted specifically for smart mobile devices become necessary. In this paper, we review three differentiating aspects for managing the power of smart mobile devices. More specifically, we emphasize the importance of platform view, user experience and platform level optimization.
Proceedings of the International Workshop on System Level Interconnect Prediction - SLIP '12, 2012
ABSTRACT Design of SoCs as well as general purpose client and server systems rely increasingly on... more ABSTRACT Design of SoCs as well as general purpose client and server systems rely increasingly on integrating available IP cores such as processing cores, accelerators and memory blocks to improve energy efficiency, reduce time to market and/or cost. As a result, the communication fabric, i.e. the glue logic between the modules and IP blocks, becomes a critical component with significant implications on system-level power, performance and area. At the same time, if not designed carefully, fabric design can adversely impact the design time and functional correctness due to its complex distributed nature. Therefore, tools and methodologies that are aware of physical constraints (area, wire congestion), design quality (power, performance) and correctness (freedom of deadlocks and livelocks) are needed for efficient design space exploration and fabric generation and design. This tutorial will overview design and optimization of communication fabrics by using examples from both the high performance CMP and SoC domains. Design methodology and outstanding challenges will be illustrated using the xPLORE framework.
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