2011 IEEE International Solid-State Circuits Conference, 2011
Here we present a new HR mixer that has significantly reduced sensitivity to mismatches in device... more Here we present a new HR mixer that has significantly reduced sensitivity to mismatches in devices operating at high frequencies. HRR for this mixer is primarily determined by resistor and capacitor matching in the low frequency IF section. Significantly improved HRR is achieved as using large resistor areas for better matching does not cause a power or bandwidth penalty in
Solid-State Circuits IEEE International Conference, 1998
Portable electronic systems require low-voltage low-power building blocks. An important building ... more Portable electronic systems require low-voltage low-power building blocks. An important building block is an A/D converter. ΔΣ ADCs provide an efficient way of trading off speed for resolution. The switched op amp (SO) technique allows design of switched-capacitor (SC) circuits at very low supply voltage without the use of multithreshold technologies or voltage multipliers to drive the switches. The basic
... 3. LOW POWER CMOS WIRELESS RECEIVER IMPLEMENTATION This section discusses a CMOS implementati... more ... 3. LOW POWER CMOS WIRELESS RECEIVER IMPLEMENTATION This section discusses a CMOS implementation example of a low power wireless receiver for GPS applications. The low IF architecture has been chosen for its good power per-formance. ... Ibn Vref,cmfb M5a ...
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002
After the success of GSM, GPS has found its way to the consumer market. GPS systems are already a... more After the success of GSM, GPS has found its way to the consumer market. GPS systems are already available in cars, watches, cell phones, etc. There is much recent research on integrating all CMOS transceiver systems on chip [1]. This CMOS GPS receiver front-end is a quadrature ...
This paper presents a continuous time quadrature ΔΣ modulator receiver. The ΔΣ AD converter imple... more This paper presents a continuous time quadrature ΔΣ modulator receiver. The ΔΣ AD converter implements a continuous time complex band-pass loopfilter. The low power requirements of the modulator allow it to be integrated into a wireless receiver. An implementation in a 1.57 GHz receiver with a 2 MHz bandwidth is shown. This receiver only needs a SAW filter and a
Proceedings of the 37th conference on Design automation - DAC '00, 2000
This paper presents an optimization algorithm that is able to significantly increase the speed of... more This paper presents an optimization algorithm that is able to significantly increase the speed of RF circuit optimizations. The algorithm consists of a series of consecutive evolutionary opti- mizations of the circuit itself and of a modeled version thereof. The speed increase arises from the difference in evaluation time between the real simulation and the fit evaluation. As circuit ap-
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
This paper presents an automated, layout-aware RF LCoscillator design tool, called CYCLONE that d... more This paper presents an automated, layout-aware RF LCoscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout. The tool combines the accuracy of device-level simulation and finite element analysis with the optimisation power of simulated annealing algorithms and is verified with experimental results.
International Conference on Computer Aided Design, 2001
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the ... more In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit,
2011 IEEE International Solid-State Circuits Conference, 2011
Here we present a new HR mixer that has significantly reduced sensitivity to mismatches in device... more Here we present a new HR mixer that has significantly reduced sensitivity to mismatches in devices operating at high frequencies. HRR for this mixer is primarily determined by resistor and capacitor matching in the low frequency IF section. Significantly improved HRR is achieved as using large resistor areas for better matching does not cause a power or bandwidth penalty in
Solid-State Circuits IEEE International Conference, 1998
Portable electronic systems require low-voltage low-power building blocks. An important building ... more Portable electronic systems require low-voltage low-power building blocks. An important building block is an A/D converter. ΔΣ ADCs provide an efficient way of trading off speed for resolution. The switched op amp (SO) technique allows design of switched-capacitor (SC) circuits at very low supply voltage without the use of multithreshold technologies or voltage multipliers to drive the switches. The basic
... 3. LOW POWER CMOS WIRELESS RECEIVER IMPLEMENTATION This section discusses a CMOS implementati... more ... 3. LOW POWER CMOS WIRELESS RECEIVER IMPLEMENTATION This section discusses a CMOS implementation example of a low power wireless receiver for GPS applications. The low IF architecture has been chosen for its good power per-formance. ... Ibn Vref,cmfb M5a ...
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002
After the success of GSM, GPS has found its way to the consumer market. GPS systems are already a... more After the success of GSM, GPS has found its way to the consumer market. GPS systems are already available in cars, watches, cell phones, etc. There is much recent research on integrating all CMOS transceiver systems on chip [1]. This CMOS GPS receiver front-end is a quadrature ...
This paper presents a continuous time quadrature ΔΣ modulator receiver. The ΔΣ AD converter imple... more This paper presents a continuous time quadrature ΔΣ modulator receiver. The ΔΣ AD converter implements a continuous time complex band-pass loopfilter. The low power requirements of the modulator allow it to be integrated into a wireless receiver. An implementation in a 1.57 GHz receiver with a 2 MHz bandwidth is shown. This receiver only needs a SAW filter and a
Proceedings of the 37th conference on Design automation - DAC '00, 2000
This paper presents an optimization algorithm that is able to significantly increase the speed of... more This paper presents an optimization algorithm that is able to significantly increase the speed of RF circuit optimizations. The algorithm consists of a series of consecutive evolutionary opti- mizations of the circuit itself and of a modeled version thereof. The speed increase arises from the difference in evaluation time between the real simulation and the fit evaluation. As circuit ap-
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
This paper presents an automated, layout-aware RF LCoscillator design tool, called CYCLONE that d... more This paper presents an automated, layout-aware RF LCoscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout. The tool combines the accuracy of device-level simulation and finite element analysis with the optimisation power of simulated annealing algorithms and is verified with experimental results.
International Conference on Computer Aided Design, 2001
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the ... more In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit,
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Papers by Peter Vancorenland