2012 IEEE Computer Society Annual Symposium on VLSI, 2012
ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integr... more ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.
2012 IEEE Computer Society Annual Symposium on VLSI, 2012
ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integr... more ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.
2010 IEEE 16th International On-Line Testing Symposium, 2010
Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to a... more Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to an insufficiency of the usually adopted functional fault models. In this sense, these fault models are no longer able to correctly reproduce the effects caused by some defects generated during the manufacturing process. In this paper, we investigate the possibility of using Built-In Current Sensors (BICSs)
2011 12th European Conference on Radiation and Its Effects on Components and Systems, 2011
ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Eve... more ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. Preliminary results investigate SET propagation in two clock networks. By using the proposed methodology, it is possible to evaluate alternative clock network designs constraints such as different number and size of buffers, clock gating and fan-out branch paths. Each solution may lead into a distinct SET susceptibility clock network map.
Nowadays, embedded Static Random Memories (SRAMs) can occupy a significant portion of the chip ar... more Nowadays, embedded Static Random Memories (SRAMs) can occupy a significant portion of the chip area and contain hundreds of millions of transistors. Due to technology scaling, functional fault models traditionally applied in SRAMs' testing have become insufficient to correctly reproduce the effects caused by some defects generated during the manufacturing process. In this paper, we investigate the possibility to use
2012 13th Latin American Test Workshop (LATW), 2012
ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Eve... more ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. We analyzed the clock tree network from SRAM arbiter layout using the proposed methodology and we found that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with lowest fan-out.
Abstract This paper presents an efficient technique for designing high defect tolerance Static Ra... more Abstract This paper presents an efficient technique for designing high defect tolerance Static Random Access Memories (SRAMs) with significantly low power consumption. The new approach requires drastically lower area overhead, simpler encoding and decoding ...
A methodology for characterization of Propagation Induced Pulse Broadening (PIPB) effects concern... more A methodology for characterization of Propagation Induced Pulse Broadening (PIPB) effects concerning the Single Event Transients (SETs) propagation within logic and routing re- sources of Flash-based Field Programmable Gate Arrays (FPGAs) is presented. Electrical-based fault injection was performed on the FPGA board and at the electrical model. Experimental results matched the electrical simulations, whichvalidate the effectiveness of the method.
2011 12th Latin American Test Workshop (LATW), 2011
ABSTRACT SpaceWire (SpW) is a well know communication standard platform proposed by European Spac... more ABSTRACT SpaceWire (SpW) is a well know communication standard platform proposed by European Space Agency (ESA). Due to its inherent properties of fault-tolerant and high-throughput, it is extensively used in avionics and satellite applications. When more than two SpW nodes communicate, a SpW Router is used. Such routers can be implemented in ASICs or in programmable devices. In order to perform fault tolerance experiments and since was not possible to find an open source of SpW Router, in this paper we present an open VHDL implementation of this router. Simulation was performed in order to validate the system, and synthesis results for ASIC and FPGA are presented. Finally, in order to analyze the SpW router behavioral when soft errors happen, a fault injection campaign was implemented and results were presented.
2012 IEEE Computer Society Annual Symposium on VLSI, 2012
ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integr... more ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.
2012 IEEE Computer Society Annual Symposium on VLSI, 2012
ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integr... more ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.
2010 IEEE 16th International On-Line Testing Symposium, 2010
Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to a... more Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to an insufficiency of the usually adopted functional fault models. In this sense, these fault models are no longer able to correctly reproduce the effects caused by some defects generated during the manufacturing process. In this paper, we investigate the possibility of using Built-In Current Sensors (BICSs)
2011 12th European Conference on Radiation and Its Effects on Components and Systems, 2011
ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Eve... more ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. Preliminary results investigate SET propagation in two clock networks. By using the proposed methodology, it is possible to evaluate alternative clock network designs constraints such as different number and size of buffers, clock gating and fan-out branch paths. Each solution may lead into a distinct SET susceptibility clock network map.
Nowadays, embedded Static Random Memories (SRAMs) can occupy a significant portion of the chip ar... more Nowadays, embedded Static Random Memories (SRAMs) can occupy a significant portion of the chip area and contain hundreds of millions of transistors. Due to technology scaling, functional fault models traditionally applied in SRAMs' testing have become insufficient to correctly reproduce the effects caused by some defects generated during the manufacturing process. In this paper, we investigate the possibility to use
2012 13th Latin American Test Workshop (LATW), 2012
ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Eve... more ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. We analyzed the clock tree network from SRAM arbiter layout using the proposed methodology and we found that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with lowest fan-out.
Abstract This paper presents an efficient technique for designing high defect tolerance Static Ra... more Abstract This paper presents an efficient technique for designing high defect tolerance Static Random Access Memories (SRAMs) with significantly low power consumption. The new approach requires drastically lower area overhead, simpler encoding and decoding ...
A methodology for characterization of Propagation Induced Pulse Broadening (PIPB) effects concern... more A methodology for characterization of Propagation Induced Pulse Broadening (PIPB) effects concerning the Single Event Transients (SETs) propagation within logic and routing re- sources of Flash-based Field Programmable Gate Arrays (FPGAs) is presented. Electrical-based fault injection was performed on the FPGA board and at the electrical model. Experimental results matched the electrical simulations, whichvalidate the effectiveness of the method.
2011 12th Latin American Test Workshop (LATW), 2011
ABSTRACT SpaceWire (SpW) is a well know communication standard platform proposed by European Spac... more ABSTRACT SpaceWire (SpW) is a well know communication standard platform proposed by European Space Agency (ESA). Due to its inherent properties of fault-tolerant and high-throughput, it is extensively used in avionics and satellite applications. When more than two SpW nodes communicate, a SpW Router is used. Such routers can be implemented in ASICs or in programmable devices. In order to perform fault tolerance experiments and since was not possible to find an open source of SpW Router, in this paper we present an open VHDL implementation of this router. Simulation was performed in order to validate the system, and synthesis results for ASIC and FPGA are presented. Finally, in order to analyze the SpW router behavioral when soft errors happen, a fault injection campaign was implemented and results were presented.
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Papers by Raul Chipana