Space Telescopes and Instrumentation 2020: Optical, Infrared, and Millimeter Wave, 2020
PLATO is an M-class mission (M3) of the European Space Agency (ESA) whose launch is scheduled in ... more PLATO is an M-class mission (M3) of the European Space Agency (ESA) whose launch is scheduled in 2026. The main aim of the mission is the detection and characterization of terrestrial exoplanets orbiting around bright solar-type star. The payload consists of 26 small telescopes: 24 “normal" cameras and 2 “fast" cameras. The huge amount of data produced by the PLATO telescopes is acquired and processed on-board by the Data Processing System (DPS) made up by various processing electronic units. The DPS of the PLATO instrument comprises the Normal and Fast DPUs (Data Processing Units) and a single ICU (Instrument Control Unit), are data routed through a SpaceWire network. The topic of this paper is the description of the architecture of the ICU and its role within the DPS, the status of the Avionic Validation Model (AVM) testing at the end of the Unit Preliminary Design Review (UPDR) performed by ESA and the results of the test of the first engineering model.
PLATO is ESA's upcoming exoplanet-hunting mission. The spacecraft has 26 cameras equipped wit... more PLATO is ESA's upcoming exoplanet-hunting mission. The spacecraft has 26 cameras equipped with a total of 104 individual CCDs, which together provide more than 2,000 megapixels, giving a combined optical sensitivity surface of 0.66m2. This is more than twice as much detector area than on ESA's Gaia mission, the largest camera ever flown in space. To measure changes in stellar brightness, the CCDs are read out at a cadence of 25 seconds, resulting in a massive amount of data that has to be processed on-board. In a pre-reduction step, hundreds of thousands of small windows of the target stars, called imagettes, are extracted from the detector arrays. This reduction process decreases the data volume down from several gigabytes to 25 MiB per acquisition period. Following this step, the remaining science data are sent to the instrument control unit (ICU), where they are processed and compressed in a lossless manner. While some science data products, such as measured backgrounds a...
2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2019
The use of reconfigurable devices, such as FPGAs, in nanosatellites allows the prototyping and ev... more The use of reconfigurable devices, such as FPGAs, in nanosatellites allows the prototyping and evaluation in flight of different categories of designs of interest to the aerospace technology. It includes blending of experimental or well-proven legacy software executing on microprocessors with out-of-core accelerators and dedicated logic circuits, or even the conversion of such software to logic circuits using high-level synthesis (HLS). An additional feature discussed in this work, which is relevant to the scientific mission of the NanosatC-BR2 nanosatellite, is the use of SRAM-based FPGA as radiation particle sensor exploiting the susceptibility of SRAM memory to bit-flips caused by radiation. The process for bit-flip recording by bitstream readback is presented as well as a set of experimental designs implemented on the FPGA for data processing. As the status of these experimental designs must be reliably tracked by a supervisory circuit implemented on the same SRAM-based FPGA, errors caused by the bit-flips must be considered. Mitigation using triple modular redundancy (TMR) is analyzed using fault injection, suggesting that a fine grain distributed TMR approach can increase mission time of the supervisory module by 8x at a target reliability of 95%, but with a penalty of 40% in the estimated total power consumption of the FPGA. Conversely, a blockwise TMR approach can increase mission time of the supervisory module by 6x at the same target reliability with no increase in the estimated total power consumption.
2014 15th Latin American Test Workshop - LATW, 2014
ABSTRACT This paper presents new experimental results about the sensitivity of an SRAM-based FPGA... more ABSTRACT This paper presents new experimental results about the sensitivity of an SRAM-based FPGA under neutron-induced and total ionizing dose effects. Both effects are combined in a practical experiment composed of a set of eight isotropic emission material blocks for neutron irradiation and a gamma rays source for ionizing dose. The experiment was performed at Instituto de Estudos Avançados, São José dos Campos, Brazil. The soft error rate has been measured from counting the bit-flip rate of the configuration memory bits and the errors at the output of the design application. Current results have shown that the soft error rate increases under neutrons when the accumulation of ionizing radiation in the device also increases until the observed doses.
2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), 2012
ABSTRACT This paper presents two adder compressors architectures addressing high-speed and low po... more ABSTRACT This paper presents two adder compressors architectures addressing high-speed and low power. Adder compressors are used to implement arithmetic circuits such as multipliers and digital signal processing units like the Fast Fourier Transform (FTT). To address the objective of high-speed and low power, it is well known that optimization efforts should be applied in all abstraction levels. In this paper are combined optimizations at logic, electrical and physical level. At the logic level, the circuit is optimized by using multiplexers instead of XOR gates to reduce delay, power and area. At the electrical level, this work presents an architecture that generate the XOR and XNOR signals simultaneously, this reduce internal glitches hence dynamic power as well. And finally at the physical level, and automatic layout generation tool (ASTRAN) is used to make the adder compressors layouts. This tool has proved to reduce power consumption and delay due to the smaller input capacitances of the complex gates generated compared to manual-designed layouts.
2012 IEEE Computer Society Annual Symposium on VLSI, 2012
ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integr... more ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.
2011 12th European Conference on Radiation and Its Effects on Components and Systems, 2011
ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Eve... more ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. Preliminary results investigate SET propagation in two clock networks. By using the proposed methodology, it is possible to evaluate alternative clock network designs constraints such as different number and size of buffers, clock gating and fan-out branch paths. Each solution may lead into a distinct SET susceptibility clock network map.
2012 13th Latin American Test Workshop (LATW), 2012
ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Eve... more ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. We analyzed the clock tree network from SRAM arbiter layout using the proposed methodology and we found that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with lowest fan-out.
This work proposes an FPGA implementation of software radio architecture for a FM modulator. The ... more This work proposes an FPGA implementation of software radio architecture for a FM modulator. The architecture is based on the Altera Nios II ® soft-processor. The frequency synthesis is performed by the digital direct synthesizer. It's a real time system that uses an audio codec WM8731 [1] to acquire the audio signal. This signal is adapted to be a parameter of the DDS. Then the digital signal produced by the DDS is transformed to the analog domain using a 10-bit video DAC ADV7123 [2].
Space Telescopes and Instrumentation 2020: Optical, Infrared, and Millimeter Wave, 2020
PLATO is an M-class mission (M3) of the European Space Agency (ESA) whose launch is scheduled in ... more PLATO is an M-class mission (M3) of the European Space Agency (ESA) whose launch is scheduled in 2026. The main aim of the mission is the detection and characterization of terrestrial exoplanets orbiting around bright solar-type star. The payload consists of 26 small telescopes: 24 “normal" cameras and 2 “fast" cameras. The huge amount of data produced by the PLATO telescopes is acquired and processed on-board by the Data Processing System (DPS) made up by various processing electronic units. The DPS of the PLATO instrument comprises the Normal and Fast DPUs (Data Processing Units) and a single ICU (Instrument Control Unit), are data routed through a SpaceWire network. The topic of this paper is the description of the architecture of the ICU and its role within the DPS, the status of the Avionic Validation Model (AVM) testing at the end of the Unit Preliminary Design Review (UPDR) performed by ESA and the results of the test of the first engineering model.
PLATO is ESA's upcoming exoplanet-hunting mission. The spacecraft has 26 cameras equipped wit... more PLATO is ESA's upcoming exoplanet-hunting mission. The spacecraft has 26 cameras equipped with a total of 104 individual CCDs, which together provide more than 2,000 megapixels, giving a combined optical sensitivity surface of 0.66m2. This is more than twice as much detector area than on ESA's Gaia mission, the largest camera ever flown in space. To measure changes in stellar brightness, the CCDs are read out at a cadence of 25 seconds, resulting in a massive amount of data that has to be processed on-board. In a pre-reduction step, hundreds of thousands of small windows of the target stars, called imagettes, are extracted from the detector arrays. This reduction process decreases the data volume down from several gigabytes to 25 MiB per acquisition period. Following this step, the remaining science data are sent to the instrument control unit (ICU), where they are processed and compressed in a lossless manner. While some science data products, such as measured backgrounds a...
2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2019
The use of reconfigurable devices, such as FPGAs, in nanosatellites allows the prototyping and ev... more The use of reconfigurable devices, such as FPGAs, in nanosatellites allows the prototyping and evaluation in flight of different categories of designs of interest to the aerospace technology. It includes blending of experimental or well-proven legacy software executing on microprocessors with out-of-core accelerators and dedicated logic circuits, or even the conversion of such software to logic circuits using high-level synthesis (HLS). An additional feature discussed in this work, which is relevant to the scientific mission of the NanosatC-BR2 nanosatellite, is the use of SRAM-based FPGA as radiation particle sensor exploiting the susceptibility of SRAM memory to bit-flips caused by radiation. The process for bit-flip recording by bitstream readback is presented as well as a set of experimental designs implemented on the FPGA for data processing. As the status of these experimental designs must be reliably tracked by a supervisory circuit implemented on the same SRAM-based FPGA, errors caused by the bit-flips must be considered. Mitigation using triple modular redundancy (TMR) is analyzed using fault injection, suggesting that a fine grain distributed TMR approach can increase mission time of the supervisory module by 8x at a target reliability of 95%, but with a penalty of 40% in the estimated total power consumption of the FPGA. Conversely, a blockwise TMR approach can increase mission time of the supervisory module by 6x at the same target reliability with no increase in the estimated total power consumption.
2014 15th Latin American Test Workshop - LATW, 2014
ABSTRACT This paper presents new experimental results about the sensitivity of an SRAM-based FPGA... more ABSTRACT This paper presents new experimental results about the sensitivity of an SRAM-based FPGA under neutron-induced and total ionizing dose effects. Both effects are combined in a practical experiment composed of a set of eight isotropic emission material blocks for neutron irradiation and a gamma rays source for ionizing dose. The experiment was performed at Instituto de Estudos Avançados, São José dos Campos, Brazil. The soft error rate has been measured from counting the bit-flip rate of the configuration memory bits and the errors at the output of the design application. Current results have shown that the soft error rate increases under neutrons when the accumulation of ionizing radiation in the device also increases until the observed doses.
2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), 2012
ABSTRACT This paper presents two adder compressors architectures addressing high-speed and low po... more ABSTRACT This paper presents two adder compressors architectures addressing high-speed and low power. Adder compressors are used to implement arithmetic circuits such as multipliers and digital signal processing units like the Fast Fourier Transform (FTT). To address the objective of high-speed and low power, it is well known that optimization efforts should be applied in all abstraction levels. In this paper are combined optimizations at logic, electrical and physical level. At the logic level, the circuit is optimized by using multiplexers instead of XOR gates to reduce delay, power and area. At the electrical level, this work presents an architecture that generate the XOR and XNOR signals simultaneously, this reduce internal glitches hence dynamic power as well. And finally at the physical level, and automatic layout generation tool (ASTRAN) is used to make the adder compressors layouts. This tool has proved to reduce power consumption and delay due to the smaller input capacitances of the complex gates generated compared to manual-designed layouts.
2012 IEEE Computer Society Annual Symposium on VLSI, 2012
ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integr... more ABSTRACT Technology scaling in deep-sub micron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.
2011 12th European Conference on Radiation and Its Effects on Components and Systems, 2011
ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Eve... more ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. Preliminary results investigate SET propagation in two clock networks. By using the proposed methodology, it is possible to evaluate alternative clock network designs constraints such as different number and size of buffers, clock gating and fan-out branch paths. Each solution may lead into a distinct SET susceptibility clock network map.
2012 13th Latin American Test Workshop (LATW), 2012
ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Eve... more ABSTRACT Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. We analyzed the clock tree network from SRAM arbiter layout using the proposed methodology and we found that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with lowest fan-out.
This work proposes an FPGA implementation of software radio architecture for a FM modulator. The ... more This work proposes an FPGA implementation of software radio architecture for a FM modulator. The architecture is based on the Altera Nios II ® soft-processor. The frequency synthesis is performed by the digital direct synthesizer. It's a real time system that uses an audio codec WM8731 [1] to acquire the audio signal. This signal is adapted to be a parameter of the DDS. Then the digital signal produced by the DDS is transformed to the analog domain using a 10-bit video DAC ADV7123 [2].
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