This paper presents the calibration methodology for our unified length/width-dependent MOSFET dra... more This paper presents the calibration methodology for our unified length/width-dependent MOSFET drain-current (I ds) model with length/width-dependent threshold-voltage (V t) model in the entire geometry/bias range based on a 0.11-Āµm CMOS technology. The model has been formulated with built-in physical effects to account for electrical characteristics of fabricated short-channel/narrow-width devices while maintaining Gummel symmetry. Through a one-iteration parameter extraction using minimum measurement data, the model can predict accurately and physically the experimental IāV data, including output conductance, transconductance, and their derivatives.
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
ABSTRACT A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-ba... more ABSTRACT A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-barrier source and drain is formulated based on the quasi-2D surface-potential solution and Miller-Good tunneling method. Essential physics due to the screening of the gate field by free carriers, which is absent in previous literatures, is included in the model. Electron and hole transports for all positive/negative gate/drain biases are modeled within the single-piece core model that scales with device geometry, body/oxide thickness, SB workfunction, and source/drain contact size. Unlike 2D numerical simulation, the proposed compact model, which is simple and fast yet accurate, is circuit-compatible and suitable for future VLSI circuit design using SB-MOS devices. The proposed modeling methodology can be easily extended to handle other promising devices such as SB silicon nanowires.
2007 7th IEEE Conference on Nanotechnology (IEEE NANO), 2007
A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped g... more A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs is developed. The surface-potential equation is derived from cylindrical Poisson equation for undoped silicon and solved iteratively with a very good initial guess to reach equation residue below 10-16 V within a few iterations. The single-piece current equation is derived and validated with numerical simulations for
Inductors that can be integrated on a silicon chip have been reported in the literature. This has... more Inductors that can be integrated on a silicon chip have been reported in the literature. This has lead to the development of silicon RF integrated circuits (RFICs) where previously discrete component inductors had to be used. Now the size of circuits can be greatly reduced with the integration of RF circuits or even complete systems on a silicon chip. This has raised enormous interest in the study of the on-chip inductor. This paper presents a comparison of various inductor expressions available in the literature. Error trends are highlighted and discussed in the 1 to 10 nH inductance region. The focus of the design is the square spiral inductor. The details of the 'new-physic' closed-form expression is found to be the most accurate expression and its implication to inductor synthesis is discussed.
Demand for mixed signal and RF devices on 0.18 Ī¼m CMOS silicon is driving the Foundry industry to... more Demand for mixed signal and RF devices on 0.18 Ī¼m CMOS silicon is driving the Foundry industry to rapidly incorporate these additional modules. This paper reports on the electrical characteristics and optimization of four mixed signal devices. Using a modular approach, Deep N-well isolated RF transistors, Native transistors, Inductors, and MIM capacitors were successfully integrated into our major Foundry Compatible 0.18 Ī¼m CMOS Logic process, without adversely affecting the digital devices. Twenty-nine different inductor structures were built and evaluated. The presence of Deep N-well implant under the inductors greatly reduced Qpeak. Self Resonance Frequency was dominated by factors controlling capacitive coupling to the substrate (line width, number of coil turns).
This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFE... more This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFET in a generic and unified description. Starting from generic Poisson solution and input voltage equation, a paradigm shift with ground-reference and source/drain by label is proposed, which is essential in formulating equations for DG FinFETs without body contact. The unified regional modeling (URM) approach is used for unified
This paper reviews the development of the MOSFET model (Xsim), for unification of various types o... more This paper reviews the development of the MOSFET model (Xsim), for unification of various types of MOS devices, such as bulk, partially/fully-depleted SOI, double-gate (DG) FinFETs and gate-all-around (GAA) silicon-nanowires (SiNWs), based on the unified regional modeling (URM) approach. The complete scaling of body doping and thickness with seamless transitions from one structure to another is achieved with the unified regional surface potential, in which other effects (such as those due to poly-gate doping and quantum-mechanical) can be incorporated. The unique features of the Xsim model and the essence of the URM approach are described.
This paper presents a methodology for extraction of the physical parameters of strained-silicon M... more This paper presents a methodology for extraction of the physical parameters of strained-silicon MOSFET from one capacitance-voltage (C-V) measurement based on physics-based compact model and conventional C-V characterization techniques. The extracted physical parameters (such as strained-silicon layer thickness and doping as well as conduction band offset) are used to create a numerical (Medici) device structure, from which the simulated C-V data is compared with the measured data as well as that from the compact model (Xsim), which validates the extraction technique. The proposed approach provides a simple yet physical means to probe into strained-silicon MOSFFET structures useful for characterize and model these devices, which are emerged as promising candidates for the enhancement and extension to conventional bulk-Si CMOS technology.
This paper presents the calibration methodology for our unified length/width-dependent MOSFET dra... more This paper presents the calibration methodology for our unified length/width-dependent MOSFET drain-current (I ds) model with length/width-dependent threshold-voltage (V t) model in the entire geometry/bias range based on a 0.11-Āµm CMOS technology. The model has been formulated with built-in physical effects to account for electrical characteristics of fabricated short-channel/narrow-width devices while maintaining Gummel symmetry. Through a one-iteration parameter extraction using minimum measurement data, the model can predict accurately and physically the experimental IāV data, including output conductance, transconductance, and their derivatives.
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
ABSTRACT A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-ba... more ABSTRACT A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-barrier source and drain is formulated based on the quasi-2D surface-potential solution and Miller-Good tunneling method. Essential physics due to the screening of the gate field by free carriers, which is absent in previous literatures, is included in the model. Electron and hole transports for all positive/negative gate/drain biases are modeled within the single-piece core model that scales with device geometry, body/oxide thickness, SB workfunction, and source/drain contact size. Unlike 2D numerical simulation, the proposed compact model, which is simple and fast yet accurate, is circuit-compatible and suitable for future VLSI circuit design using SB-MOS devices. The proposed modeling methodology can be easily extended to handle other promising devices such as SB silicon nanowires.
2007 7th IEEE Conference on Nanotechnology (IEEE NANO), 2007
A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped g... more A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs is developed. The surface-potential equation is derived from cylindrical Poisson equation for undoped silicon and solved iteratively with a very good initial guess to reach equation residue below 10-16 V within a few iterations. The single-piece current equation is derived and validated with numerical simulations for
Inductors that can be integrated on a silicon chip have been reported in the literature. This has... more Inductors that can be integrated on a silicon chip have been reported in the literature. This has lead to the development of silicon RF integrated circuits (RFICs) where previously discrete component inductors had to be used. Now the size of circuits can be greatly reduced with the integration of RF circuits or even complete systems on a silicon chip. This has raised enormous interest in the study of the on-chip inductor. This paper presents a comparison of various inductor expressions available in the literature. Error trends are highlighted and discussed in the 1 to 10 nH inductance region. The focus of the design is the square spiral inductor. The details of the 'new-physic' closed-form expression is found to be the most accurate expression and its implication to inductor synthesis is discussed.
Demand for mixed signal and RF devices on 0.18 Ī¼m CMOS silicon is driving the Foundry industry to... more Demand for mixed signal and RF devices on 0.18 Ī¼m CMOS silicon is driving the Foundry industry to rapidly incorporate these additional modules. This paper reports on the electrical characteristics and optimization of four mixed signal devices. Using a modular approach, Deep N-well isolated RF transistors, Native transistors, Inductors, and MIM capacitors were successfully integrated into our major Foundry Compatible 0.18 Ī¼m CMOS Logic process, without adversely affecting the digital devices. Twenty-nine different inductor structures were built and evaluated. The presence of Deep N-well implant under the inductors greatly reduced Qpeak. Self Resonance Frequency was dominated by factors controlling capacitive coupling to the substrate (line width, number of coil turns).
This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFE... more This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFET in a generic and unified description. Starting from generic Poisson solution and input voltage equation, a paradigm shift with ground-reference and source/drain by label is proposed, which is essential in formulating equations for DG FinFETs without body contact. The unified regional modeling (URM) approach is used for unified
This paper reviews the development of the MOSFET model (Xsim), for unification of various types o... more This paper reviews the development of the MOSFET model (Xsim), for unification of various types of MOS devices, such as bulk, partially/fully-depleted SOI, double-gate (DG) FinFETs and gate-all-around (GAA) silicon-nanowires (SiNWs), based on the unified regional modeling (URM) approach. The complete scaling of body doping and thickness with seamless transitions from one structure to another is achieved with the unified regional surface potential, in which other effects (such as those due to poly-gate doping and quantum-mechanical) can be incorporated. The unique features of the Xsim model and the essence of the URM approach are described.
This paper presents a methodology for extraction of the physical parameters of strained-silicon M... more This paper presents a methodology for extraction of the physical parameters of strained-silicon MOSFET from one capacitance-voltage (C-V) measurement based on physics-based compact model and conventional C-V characterization techniques. The extracted physical parameters (such as strained-silicon layer thickness and doping as well as conduction band offset) are used to create a numerical (Medici) device structure, from which the simulated C-V data is compared with the measured data as well as that from the compact model (Xsim), which validates the extraction technique. The proposed approach provides a simple yet physical means to probe into strained-silicon MOSFFET structures useful for characterize and model these devices, which are emerged as promising candidates for the enhancement and extension to conventional bulk-Si CMOS technology.
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Papers by Guan Huei See