ECL: a specification environment for system-level design

G Berry, E Harcourt, L Lavagno, E Sentovich - … Systems Design Languages, 2001 - Springer
ECL is a good candidate for specification of new behavior in system-level design tools
such as Cadence's Cierto VCC tool [l]. ECL is especially targeted for specification of control …

[BOOK][B] Designing embedded systems with the Signal programming language: synchronous, reactive specification

A Gamatié - 2009 - books.google.com
I am very pleased to play even a small part in the publication of this book on the SIGNAL
language and its environment POLYCHRONY. I am sure it will be a s-ni? cant milestone in the …

Pact hdl: A c compiler targeting asics and fpgas with power and performance optimizations

A Jones, D Bagchi, S Pal, X Tang… - Proceedings of the …, 2002 - dl.acm.org
… The Esterel-C Language (ECL) developed at Cadence Berkeley Laboratories is an HDL and
compilation suite based on the C language[15]. CoWare, Inc. has developed the N2C layer …

PACT HDL: a compiler targeting ASICs and FPGAs with power and performance optimizations

A Jones, D Bagchi, S Pal, P Banerjee… - Power aware …, 2002 - Springer
… The Esterel-C Language (ECL) developed at Cadence Berkeley Laboratories is an HDL and
compilation suite based on the C language[11]. CoWare, Inc. has developed the N2C layer …

Designing Embedded Systems with the SIGNAL Programming

A Gamatié - Springer
This book has been written to present the design of embedded systems in safetycritical
domains such as automotive vehicles, avionics, and nuclear power plants, by using the SIGNAL …

An overview of a compiler for mapping MATLAB programs onto FPGAs

P Banerjee - Proceedings of the 2003 Asia and South Pacific Design …, 2003 - dl.acm.org
This paper describes a behavioral synthesis tool called the MATCH compiler developed as
part of the DARPA Adaptive Computing Systems program. The MATCH compiler reads in …

Overview of a compiler for synthesizing MATLAB programs onto FPGAs

P Banerjee, M Haldar, A Nayak, V Kim… - … Transactions on Very …, 2004 - ieeexplore.ieee.org
This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level
descriptions of digital signal processing (DSP) applications written in MATLAB, and …

[PDF][PDF] Method for automatic generation of RTL in VHDL using decision diagrams

S Stankovic, J Takala, J Astola - Proc. The 2006 International …, 2006 - researchgate.net
In recent years, decision diagrams have earned a prominent place in the field of logic design
as means of efficient representation of switching function, in terms of needed storage space …

A behavioral synthesis tool for exploiting fine grain parallelism in FPGAs

P Banerjee, M Haldar, A Nayak, V Kim… - … Workshop on Distributed …, 2002 - Springer
… that translated from languages such as C or C++ into VHDL and Verilog, this paper describes
a compiler that takes behavioral MATLAB descriptions (the default language of DSP design…

[PDF][PDF] Method for automatic generation of branching programs using decision diagrams

S Stankovic, J Astola - Proc. The, 2007 - researchgate.net
… We present an illustrative example of a branching program generated for a given boolean
function. Possibilities of generalization of proposed method to other types of decision …