Article

Reducing cache energy consumption by tag encoding in embedded processors

Authors:

Mingming Zhang,

Xiaotao Chang, and

Ge ZhangAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

Pages 367 - 370

https://doi.org/10.1145/1283780.1283860

Published: 27 August 2007 Publication History

Abstract

This paper presents a new technique eliminating redundant cache tag and data accesses to reduce energy consumption. We assign a register to each tag in a cache to represent its state. Before starting an access, we can check the tag states in the target cache set to determine which way(s) should be accessed and which should not. Through this method, almost all the accesses in the I-cache can be directed to the target cache way immediately for most benchmark programs. For a 2-way set-associative cache, the energy consumption can be reduced by 76.6% compared with conventional cache architecture, and by 39.8% compared with Block Buffering, a simple but well-known technique. Besides, this approach does not require any special circuitry internal to the cache RAM such as row or column activation mechanisms. This is considered an important advantage in industry because of its easy implementation.

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Cited By

Wu WZhu QWang FLin RQi F(2020)Compiler Optimizing for Power Efficiency of On-Chip MemoryAdvanced Computer Architecture10.1007/978-981-15-8135-9_21(290-303)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_21
Wang LWang D(2016)Way prediction set-associative data cache for low power digital signal processors2016 IEEE 13th International Conference on Signal Processing (ICSP)10.1109/ICSP.2016.7877886(508-512)Online publication date: Nov-2016
https://doi.org/10.1109/ICSP.2016.7877886
Bunse CHöpfner HKlingert SMansour ERoychoudhury S(2014)Energy Aware Database ManagementEnergy-Efficient Data Centers10.1007/978-3-642-55149-9_4(40-53)Online publication date: 2014
https://doi.org/10.1007/978-3-642-55149-9_4
Show More Cited By

Index Terms

Reducing cache energy consumption by tag encoding in embedded processors
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Conferences

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 27 August 2007

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August 27 - 29, 2007

OR, Portland, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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August 5 - 7, 2024

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Cited By

Wu WZhu QWang FLin RQi F(2020)Compiler Optimizing for Power Efficiency of On-Chip MemoryAdvanced Computer Architecture10.1007/978-981-15-8135-9_21(290-303)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_21
Wang LWang D(2016)Way prediction set-associative data cache for low power digital signal processors2016 IEEE 13th International Conference on Signal Processing (ICSP)10.1109/ICSP.2016.7877886(508-512)Online publication date: Nov-2016
https://doi.org/10.1109/ICSP.2016.7877886
Bunse CHöpfner HKlingert SMansour ERoychoudhury S(2014)Energy Aware Database ManagementEnergy-Efficient Data Centers10.1007/978-3-642-55149-9_4(40-53)Online publication date: 2014
https://doi.org/10.1007/978-3-642-55149-9_4
Quanquan Li Qi Wang Tiejun Zhang Donghui Wang Chaohuan Hou (2013)Low power instruction cache design based on branch execution tracks2013 IEEE 10th International Conference on ASIC10.1109/ASICON.2013.6811822(1-4)Online publication date: Oct-2013
https://doi.org/10.1109/ASICON.2013.6811822
Cho HChoi JJhang SJhon C(2012)Low Power Instruction Cache with Word Selective Line BufferProceedings of the 2012 IEEE 15th International Conference on Computational Science and Engineering10.1109/ICCSE.2012.37(215-222)Online publication date: 5-Dec-2012
https://dl.acm.org/doi/10.1109/ICCSE.2012.37
Berticelli Lo TBeck ARutzig MCarro L(2010)A low-energy approach for context memory in reconfigurable systems2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)10.1109/IPDPSW.2010.5470745(1-8)Online publication date: Apr-2010
https://doi.org/10.1109/IPDPSW.2010.5470745
Bunse CHopfner HMansour ERoychoudhury S(2009)Exploring the Energy Consumption of Data Sorting Algorithms in Embedded and Mobile EnvironmentsProceedings of the 2009 Tenth International Conference on Mobile Data Management: Systems, Services and Middleware10.1109/MDM.2009.103(600-607)Online publication date: 18-May-2009
https://dl.acm.org/doi/10.1109/MDM.2009.103
Kalyan TMutyam MNarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Word-interleaved cacheProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393991(265-270)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1393991

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