research-article

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

Authors:

Jason Helge Anderson,

Jonathan Scott RoseAuthors Info & Claims

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

Pages 227 - 236

https://doi.org/10.1145/1950413.1950457

Published: 27 February 2011 Publication History

Abstract

The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. In this paper, we present a new logic block description language that can depict complex intra-block interconnect, hierarchy and modes of operation. These features are necessary to support modern and future FPGA complex soft logic blocks, memory and hard blocks. The key part of the CAD flow associated with this complexity is the packer, which takes the logical atomic pieces of the complex blocks and groups them into whole physical entities. We present an area-driven generic packing tool that can pack the logical atoms into any heterogeneous FPGA described in the new language, including many different kinds of soft and hard logic blocks. We gauge its area quality by comparing the results achieved with a lower bound on the number of blocks required, and then illustrate its explorative capability in two ways: on fracturable LUT soft logic architectures, and on hard block memory architectures. The new infrastructure attaches to a flow that begins with a Verilog front-end, permitting the use of benchmarks that are significantly larger than the usual ones, and can target heterogenous FPGAs.

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Index Terms

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
1. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
    2. Logic synthesis
      1. Circuit optimization

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Published In

cover image ACM Conferences

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

February 2011

300 pages

ISBN:9781450305549

DOI:10.1145/1950413

General Chair:
John Wawrzynek
University of California, Berkeley, USA
,
Program Chair:
Katherine Compton
University of Wisconsin-Madison, USA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 February 2011

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FPGA '11

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FPGA '11: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2011

CA, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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The 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Cited By

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https://dl.acm.org/doi/10.1145/3665283.3665300
Kissich MBaunach M(2024)FazyRV: Closing the Gap between 32-Bit and Bit-Serial RISC-V Cores with a Scalable ImplementationProceedings of the 21st ACM International Conference on Computing Frontiers10.1145/3649153.3649195(240-248)Online publication date: 7-May-2024
https://dl.acm.org/doi/10.1145/3649153.3649195
Shahrouz SBetz V(2024)The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAs2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00015(33-42)Online publication date: 2-Sep-2024
https://doi.org/10.1109/FPL64840.2024.00015
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Bhandari JThalakkattu Moosa ATan BPilato CGore GTang XTemple SGaillardon PKarri R(2021)Exploring eFPGA-based Redaction for IP Protection2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643548(1-9)Online publication date: 1-Nov-2021
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Xu YXu N(2021)FPGA autotuning optimization based on structural equation modelingProcedia Computer Science10.1016/j.procs.2021.02.041183(132-138)Online publication date: 2021
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