research-article

Investigating modern layout representations for improved 3d design automation

Authors:

Robert Fischbach,

Johann KnechtelAuthors Info & Claims

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Pages 337 - 342

https://doi.org/10.1145/1973009.1973076

Published: 02 May 2011 Publication History

Abstract

The current trend towards 3D integration requires new layout representations specifically designed to take 3D-specific constraints into account and to facilitate efficient design algorithms. We observe that it is difficult to compare and evaluate these layout-specific data structures. In this paper, we first present a detailed investigation of modern layout representations while analyzing their solution space and their characteristics, such as redundancy and reachability. Our investigation reveals their potential for 3D applications but also shows open challenges to be considered for (future) representations. Thus, we also provide guidelines for designing efficient layout representations. Finally, we release our investigation methodology as open-source tool, thus providing interested researchers with the opportunity to conduct reasonable evaluations on their own.

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Cited By

Lin JYang J(2017)Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269590036:11(1856-1868)Online publication date: Nov-2017
https://doi.org/10.1109/TCAD.2017.2695900
Knechtel JLienig JYoung EOzdal M(2016)Physical Design Automation for 3D Chip StacksProceedings of the 2016 on International Symposium on Physical Design10.1145/2872334.2872335(3-10)Online publication date: 3-Apr-2016
https://dl.acm.org/doi/10.1145/2872334.2872335
Bermudez GRojas LRodriguez J(2014)Optimization models in layout2014 9th Iberian Conference on Information Systems and Technologies (CISTI)10.1109/CISTI.2014.6876978(1-6)Online publication date: Jun-2014
https://doi.org/10.1109/CISTI.2014.6876978
Show More Cited By

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cover image ACM Conferences

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

May 2011

496 pages

ISBN:9781450306676

DOI:10.1145/1973009

General Chairs:
David Atienza
EPFL, Switzerland
,
Yuan Xie
Penn State University, USA
,
Program Chairs:
Jose L. Ayala
Federal University of Pernambuco, Brazil
,
Ken Stevens
University of Utah, USA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE CASS

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Association for Computing Machinery

New York, NY, United States

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Published: 02 May 2011

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GLSVLSI '11

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GLSVLSI '11: Great Lakes Symposium on VLSI 2011

May 2 - 4, 2011

Lausanne, Switzerland

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Lin JYang J(2017)Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269590036:11(1856-1868)Online publication date: Nov-2017
https://doi.org/10.1109/TCAD.2017.2695900
Knechtel JLienig JYoung EOzdal M(2016)Physical Design Automation for 3D Chip StacksProceedings of the 2016 on International Symposium on Physical Design10.1145/2872334.2872335(3-10)Online publication date: 3-Apr-2016
https://dl.acm.org/doi/10.1145/2872334.2872335
Bermudez GRojas LRodriguez J(2014)Optimization models in layout2014 9th Iberian Conference on Information Systems and Technologies (CISTI)10.1109/CISTI.2014.6876978(1-6)Online publication date: Jun-2014
https://doi.org/10.1109/CISTI.2014.6876978
Knechtel JYoung ELienig J(2014)Structural planning of 3D-IC interconnects by block alignment2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2014.6742866(53-60)Online publication date: Jan-2014
https://doi.org/10.1109/ASPDAC.2014.6742866
Fischbach RKnechtel JLienig JKoh CSze C(2013)Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systemsProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451921(11-16)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451921
Budhathoki PKnechtel JHenschel AElfadel I(2013)Integration of thermal management and floorplanning based on three-dimensional layout representations2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)10.1109/ICECS.2013.6815572(962-965)Online publication date: Dec-2013
https://doi.org/10.1109/ICECS.2013.6815572

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