poster

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

Authors:

Pascal Andreas Meinerzhagen,

Jürg Treichler,

Andreas Peter BurgAuthors Info & Claims

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Pages 343 - 346

https://doi.org/10.1145/1973009.1973078

Published: 02 May 2011 Publication History

Abstract

This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. A memory macro in 90-nm CMOS technology including multilevel write and read circuits is proposed and analyzed with respect to its read failure probability due to within-die process variations by means of Monte Carlo simulations.

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Cited By

Frankel BSarfati ERossi DWimer S(2023)Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAMIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.323186670:4(1605-1612)Online publication date: Apr-2023
https://doi.org/10.1109/TCSI.2022.3231866
Frankel BHerman RWimer S(2018)Queuing-Based eDRAM Refreshing for Ultra-Low Power ProcessorsIEEE Transactions on Computers10.1109/TC.2018.281147067:9(1331-1340)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1109/TC.2018.2811470
Meinerzhagen PTeman AGiterman REdri NBurg AFish AMeinerzhagen PTeman AGiterman REdri NBurg AFish A(2017)Aggressive Technology and Voltage Scaling (Down to the Subthreshold Domain)Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_6(91-111)Online publication date: 7-Jul-2017
https://doi.org/10.1007/978-3-319-60402-2_6
Show More Cited By

Index Terms

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems
1. Hardware

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cover image ACM Conferences

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

May 2011

496 pages

ISBN:9781450306676

DOI:10.1145/1973009

General Chairs:
David Atienza
EPFL, Switzerland
,
Yuan Xie
Penn State University, USA
,
Program Chairs:
Jose L. Ayala
Federal University of Pernambuco, Brazil
,
Ken Stevens
University of Utah, USA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 02 May 2011

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GLSVLSI '11: Great Lakes Symposium on VLSI 2011

May 2 - 4, 2011

Lausanne, Switzerland

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Frankel BSarfati ERossi DWimer S(2023)Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAMIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.323186670:4(1605-1612)Online publication date: Apr-2023
https://doi.org/10.1109/TCSI.2022.3231866
Frankel BHerman RWimer S(2018)Queuing-Based eDRAM Refreshing for Ultra-Low Power ProcessorsIEEE Transactions on Computers10.1109/TC.2018.281147067:9(1331-1340)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1109/TC.2018.2811470
Meinerzhagen PTeman AGiterman REdri NBurg AFish AMeinerzhagen PTeman AGiterman REdri NBurg AFish A(2017)Aggressive Technology and Voltage Scaling (Down to the Subthreshold Domain)Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_6(91-111)Online publication date: 7-Jul-2017
https://doi.org/10.1007/978-3-319-60402-2_6
Meinerzhagen PTeman AGiterman REdri NBurg AFish AMeinerzhagen PTeman AGiterman REdri NBurg AFish A(2017)Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior ArtGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_2(13-26)Online publication date: 7-Jul-2017
https://doi.org/10.1007/978-3-319-60402-2_2
Kazimirsky AWimer S(2016)Opportunistic Refreshing Algorithm for eDRAM MemoriesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2016.260053863:11(1921-1932)Online publication date: Nov-2016
https://doi.org/10.1109/TCSI.2016.2600538
Meinerzhagen PBonetti AKarakonstantis GRoth CGiirkaynak FBurg A(2015)Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder2015 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2015.7168911(1426-1429)Online publication date: May-2015
https://doi.org/10.1109/ISCAS.2015.7168911
Meinerzhagen PTeman AGiterman RBurg AFish A(2013)Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology ScalingJournal of Low Power Electronics and Applications10.3390/jlpea30200543:2(54-72)Online publication date: 29-Apr-2013
https://doi.org/10.3390/jlpea3020054
Meinerzhagen PTeman AMordakhay ABurg AFish A(2012)A sub-VT 2T gain-cell memory for biomedical applications2012 IEEE Subthreshold Microelectronics Conference (SubVT)10.1109/SubVT.2012.6404318(1-3)Online publication date: Oct-2012
https://doi.org/10.1109/SubVT.2012.6404318
Khalid MMeinerzhagen PBurg A(2012)Replica bit-line technique for embedded multilevel gain-cell DRAM10th IEEE International NEWCAS Conference10.1109/NEWCAS.2012.6328960(77-80)Online publication date: Jun-2012
https://doi.org/10.1109/NEWCAS.2012.6328960
Teman AMeinerzhagen PBurg AFish A(2012)Review and classification of gain cell eDRAM implementations2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel10.1109/EEEI.2012.6377022(1-5)Online publication date: Nov-2012
https://doi.org/10.1109/EEEI.2012.6377022

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