Perturb and simplify: multilevel Boolean network optimizer

2007

In this paper we present the application of our ATPGbased design rewiring approach to multi-level combinational logic circuit optimization. At every step of this optimization procedure, we introduce a design error by removing the logic that violates the optimization constraint(s) and then we attempt to correct the design by modifying the logic somewhere else. We give heuristics and describe the application of this method to delay optimization and to design for low power. Experiments are also presented to support the potential of our method. Ivor Ting Andreas Veneris Magdy S. Abadir Alcatel University of Toronto Motorola 4190 Still Creek Drive Dept ECE and CS 7700 W. Parmer Burnaby, BC V5C 6C6 Toronto, ON M5S 3G4 Austin, TX 78729 ivor.ting@alcatel.com veneris@eecg.toronto.edu m.abadir@motorola.com

Proc. of …, 2000

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware, 2000

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings., 2004

2005

2005

IEEE Transactions on Computers, 1978

VLSI Design, 1997

Jetzt kommt es auf uns an: In vielen erfolgreichen wissenschaftlichen Sachbüchern schreiben die Autorinnen und Autoren jetzt auffällig viel über sich selbst. Muss das sein? In: Süddeutsche Zeitung, 18.6.2024, S. 10.