Quick placement with geometric constraints

Quick Placement with Geometric Constraints Enrico Malavasi, Joseph L. Ganley and Edoardo Charbon Cadence Design Systems, Inc. - San Jose, CA, 95134 Abstract In this paper an original constraint-driven placement tool targeted for full-custom mixed-signal design is described. One of its main objectives is to quickly obtain feasible layout con gurations, and explore eciently the e ect of di erent sets of constraints in an interactive environment. By using direct-approach algorithms, all feasible constraints are met by construction. Overconstraints are detected, and quick feedback is given to the user about infeasible requirements. Good results have been obtained on a signi cant set of industrial-strength test cases. orientation processor Find best placement QP−based force−dir. <N iterations 1. Introduction Most of the existing approaches to performance-driven layout design, in particular in the mixed-signal and analog domain, have focused on full automation of the design process. In particular the fundamental work done at Berkeley [1] and at Carnegie Mellon [2] has contributed to an understanding of the issues related to constraint management and enforcement in layout. However, as the circuit complexity and the number of constraints grow, the quality and density of automatic solutions are still often inadequate. With high-performance mixed-signal full-custom designs, a combination of manual and automatic design must be used. The role of automatic tools is to provide a fast exploration of the solution space, to be followed by manual ne tuning. In particular in the case of constraint-driven placement, the most common approach used is simulated annealing [3, 4]. The time it requires to achieve a significant result is often in the order of several minutes to a few hours, which is often unacceptable in an interactive environment. On the other hand, the existing direct approaches, such as force-directed placement [5, 6], take into account few or no geometric constraints on the layout. In this paper a new constraint-driven placement tool for fullcustom design called Device-Level Placer (DLP) is described. One of the main targets in its implementation was to provide the user with a quick way to obtain feasible layout con gurations, and explore eciently the e ect of applying di erent sets of constraints. Hence, a placement of all components that is consistent with a complex set of geometric constraints and oor-plan requirements must be found within a reasonable amount of time. Our target was to obtain a solution within a few seconds for simple cells of 10 to 50 components, and no more than a few minutes for circuits with a few hundred components. DLP has been implemented using a direct approach based on a force-directedplacement augmented by a min-cut partitioner, modi ed to guarantee the enforcement of geometric constraints. The algorithms used, Quadratic Programming (QP) [7] for the forcedirected placement, and the Fiduccia-Mattheyses (FM) [8] algorithm for min-cut, have been combined in the past for placement [5, 6]. In our approach an entire set of geometric constraints is taken into account and enforced. Infeasible con gurations, due to overconstraints, are detected, and quick feedback is given to the user about the infeasibleconstraints. We are not aware of any other approach to placement, using direct-approach algorithms, which is able to guarantee to meet such a large set of geometric constraints. The results obtained on a signi cant set of industrial-strength test cases show that this approach produces good quality placement even with a large number of simultaneous constraints. optimizer Set correct orientations Spread FM−based components over min−cut available area Optimize area usage Minimize wire length Remove overlaps Fig. 1. Structure of DLP. The loop involving QP and FM has at most N iteration, where N is the number of components. This paper is organized as follows. Section 2 provides an overview of the Device-Level Placer structure. In Section 3 the geometric constraint categories are analyzed, and the corresponding enforcement techniques are described. Implementation and results are shown in Section 4. Conclusions are presented in Section 5. 2. DLP The Device-LevelPlacer (DLP) is an automaticconstraint-driven placement tool, targeted for mixed-signal device- and block-level design. The structure of DLP is illustrated in Figure 1. It is made of three phases: In the rst phase, an orientation processor sets correct orientations on all components, consistent with the entire set of geometric constraints. Orientation overconstraints are detected in this phase, and feedback is provided to the user about infeasible constraints, which will be ignored during placement. The second phase iterates between two algorithms: (a) a QP-based force-directed placement algorithm, which places all components minimizing the length of interconnections; (b) a min-cut partitioner based on the FM algorithm, which optimizes the result obtained in (a), spreading as uniformly as possible the components over the area available for placement. The number of iterations is never greater than N, which is the total number of components in the layout. Both algorithms enforce all constraints on the relative and absolute positions of the components. The techniques used are described in Section 3. This phase does not change the component orientations. The third phase is an iterative optimizer, trying to minimize the wire length, to further optimize the area usage, and to remove any remaining overlaps. In principle this can be seen as a low-temperature simulated annealing algorithm. The set of moves maintains all components within short distance from their initial placement, and no constraint violations are allowed. Notice that the rst two phases enforce all geometric constraints, [symmetry] 10um B x A vert. align D C symmetry Fig. 2. Overconstraint generated by the combination of a symmetry constraint, alignment and minimum spacing. respectively on orientation and position. In the third phase, on the contrary, the optimizer expects all constraints to be already enforced by the previous phases, and therefore it preserves the constraints, rather than enforcing them. The second phase replicates the approach proposed for quick placement in [5, 6]. However, original modi cations have been added to the original algorithm to enforce position constraints. Moreover, the combination of all three phases is necessary to enforce the full set of geometric constraints, as described in detail in Section 3. Overconstraints An overconstraint is a con ict between a set of two or more incompatible constraints, hence the entire set of constraints cannot be simultaneously enforced. As an example, consider the case where four components A, B, C, D are de ned, and the following four constraints are speci ed:  A and B must be symmetric with respect to a vertical axis x.  C and D must be symmetric with respect to the same axis x.  A and C must be aligned along the vertical direction (same X coordinate)  The horizontal spacing between B and D must be no less than 10m. In this situation, illustrated in Figure 2, no con guration exists for the four components, that satis es all constraints. For instance, the con guration shown in Figure 2 violates the symmetry constraint between A and B, and satis es the other three constraints. Overconstraints may be dicult to detect before placement, in particular when they are due to the combination of more than two constraints. A policy to deal with overconstraints must be part of all constraint-driventools. In DLP, all constraints are given numerical priorities. DLP enforces a maximum set of constraints using the following strategy: only the constraints with lowest priority are violated, and the user is promptly noti ed when violations occur, and about which constraints are not enforced. Priorities are dened by default based on the constraint category, and the user can override the default by assigning di erent priorities to individual constraints. Setting constraint priorities is a critical design choice, because in case of overconstraints the constraints with lowest priority will not be met. Often this choice is not simple, and a trial-and-error approach is necessary. In this situation, a fast automatic constraintdriven placement tool becomes an invaluable help to explore different scenarios and get feedback about the feasibility of di erent constraint sets. 3. Geometric Constraints Geometric constraints are de ned as restrictions on the absolute and relative position and orientation of layout components. Coordinates can be those of the center or edges of the component bounding box, or of edges of its layers. In what follows we will ignore the speci c reference, since at least in principle all references are equivalent to one another, plus a component-speci co set. Geometric constraints are required to accomplish the following tasks: 1. To drive automatic tools toward a prede ned oor-plan, or to limit the search space during placement, in a trial and error approach. 2. To specify correlations between components, for instance in order to minimize mismatch or thermal noise. 3. To implement high-level speci cations. Geometric constraints may be generated indirectly through automatic constraint translation based on high-level design performance speci cations [9, 10]. In DLP, geometric constraints are classi ed into six categories: Fixed X/Y/, Spacing, Firm Groups, Relative Orientation, Alignment, and Symmetries. These categories cover most of the geometric requirements in a layout system. More complex constraints can be built as combinations of those categories. As an example, consider a matching constraint on a set of components. As shown in [11], matching can be enforced by requiring the components to be within a max distance from each other (max spacing constraint) and to have the same orientation (Relative Orientation constraint). Optional requirements might include alignment between the components, or rm-grouping if their relative position has been determined by some module generator. In what follows, for each category we describe the constraint semantic and the enforcement technique implemented in DLP. Fixed X/Y/ A Fixed constraint applies to one component. It speci es the exact value of the position of the component, and its absolute orientation with respect to the reference coordinate system. It is represented by two coordinates X and Y, and an orientation . Any of these three parameters can be left unde ned, although at least one of the three must be de ned for the constraint to be meaningful. The enforcement of Fixed constraints is straightforward:  The orientation  is set by the orientation processor, and never modi ed afterwards.  The coordinates X and Y, if xed, are constants for the QP solver, that is the row and column of the corresponding components are removed from the system.  The partitioner treats the xed X/Y components as unmovable within the side each of them happens to fall in when the cut is drawn.  The optimizer does not modify any of the xed component's coordinates or orientation. Spacing The spacing between components is de ned as the range between the minimum and maximum distance allowed between their reference points, in either orthogonal direction. A minimum distance d between components means that they cannot be placed at a distance less than d. A maximum distance D instead means that they cannot be placed at a distance greater than D. If the minimum spacing is not speci ed it defaults to zero, while the default for the maximum is in nity. Di erent spacing may be required in the X or Y direction respectively. Spacing constraints are enforced by the partitioner and by the optimizer:  The partitioner applies the following rule: components with a minimum distance requirement d can be placed within the same partition only if its size is at least d. Analogously, components with a maximum distance constraint D must be placed within the same partition of a cut, unless the max distance between components in opposite sides of the cut is no more than D.  The optimizer always keeps components spaced by values within their spacing constraint range. Firm Groups Move in opposite directions A Firm Group is a constraint involving two or more components. The relative position and orientation of the components cannot be changed, although the group as a whole can move and rotate in the layout space. A Firm Group behaves like one component from the perspective of the placement tool. The enforcement of this constraint is in principle straightforward: all the components in the group are substituted by one equivalent component in all phases of the placement. Although simple in principle, the implementation can be quite complex, because it involves a translation of all the constraints involving the original components of the group (in particular alignments, symmetry etc.) into suitable constraints on the equivalent component for DLP. Slide together along symm. axis Rotate in opposite directions Relative Orientation The Relative Orientation constraint applies to sets of two or more components, and as the name indicates it corresponds to a requirement on the relative orientation between them. It can be any of the following:  All components have the same orientation  Each two components on the set have either the same orientation, or mirrored orientations.  The components in the set are exactly two, and their orientations must be mirrored with respect to each other. Since the QP and the partitioner do not modify the components' orientation, this constraint is enforced through the orientation processor and the optimizer only:  The orientation processor determines an orientation for all components, which is compatible with their relative orientation requirement.  The optimizer can modify the components' orientations, individually and as a group, to optimize area occupation and remove overlaps, while correctly preserving their relative orientation. Alignment Alignment constraints apply to sets of two or more components. The constraint implies that all components keep their reference point either on the same X coordinate (vertical alignment) or on the same Y coordinate (horizontal alignment). The enforcement of alignment is complex and involves several phases of the placement:  The matrix used by the QP algorithm is simpli ed by substituting the X coordinate (if vertical alignment) or the Y coordinate (with horizontal alignment) of all components with the coordinate of one of them chosen arbitrarily.  In the partitioner, when a cut is drawn parallel to the alignment direction, all the aligned components must be kept on the same side of the cut. If the cut is in the opposite direction, the partition must keep track of the aligned components, and guarantee that further cuts will maintain them aligned.  Alignment is preserved by the optimizer via composite moves. When an aligned component is moved in a direction orthogonal to alignment, all the other components aligned with it must be moved in the same direction, and by the same amount. Symmetries In a symmetry constraint, we de ne an axis (vertical or horizontal), self-symmetric components, and component pairs. The position of the axis can be xed or variable. Self-symmetric components are required to keep one coordinate of the center of their bounding box, X for a vertical axis, Y for a horizontal axis, on the axis itself. Notice that if the position of the axis is xed, this is equivalent to a Fixed X or Fixed Y constraint on the component respectively. The two components in a pair are required to:  Keep the same distance from the symmetry axis  Keep on opposite sides of the axis  Be aligned in the direction orthogonal to the axis A C Slide along symm. axis B Fig. 3. Structure of a symmetry constraint with a vertical axis, one self-symmetric component, and one pair. Have mirrored relative orientation across the axis Symmetries are probably the most complexgeometric constraints to deal with. Figure 3 shows the structure of a symmetry constraint with a vertical axis, one self-symmetric component B, and one pair (A,C). The enforcement of symmetries in DLP is done with the following procedure:  The orientation processor sets mirrored orientations on the components of each pair.  The axis is added to the system as a new component. If the axis position is xed, a Fixed X/Y constraint is added to the system for the axis itself.  The partitioner draws rst a cut along each of the symmetry axes. Following cuts are executed in parallel on each side of the symmetry axis, for each partition containing one of the symmetric components.  The optimizer does not disrupt symmetric objects, although it can change their position and their orientations. Symmetry is preserved through composite moves, illustrated by the arrows shown in Figure 3. Components in a pair can slide parallel to the axis, or move simultaneously in opposite directions orthogonal to it. They can only rotate simultaneously by mirrored angles. Self-symmetriccomponentscan only slide along the axis direction. The entire set of symmetric components for the same axis can move together (like in a Firm Group) if the axis position is not xed.  4. Experimental Results DLP is a new product in the Device-LevelEditor (DLE) environment, within the VirtuosoTM Layout System. It has been tested on a large set of full-custom cells, some of which were provided by customers with their original speci cations. Table 1 summarizes the performance of DLP on a sample of mixed-signal circuits. For each circuit we have reported the size, the CPU time, and the categories of constraints applied. The initial area assigned to each circuit was assigned by the circuit designer. The optimizer was run for the minimum amount necessary to ensure the removal of all overlaps. In no instance was it necessary to run the optimizer for more than 5 seconds. The CPU time seems to be loosely correlated with the number and type of constraints. The optimizer's Vdd Vdd Vpb P1 R21 R22 P2 P1 P2 Q8 In Out N3 N2 Vpb In N6 Vnb R21 R22 N2 C13 Vqb Vnb Vqb N6 Q9 R11 Q10 N3 N7 Out Q8 Q9 N7 Q10 C13 R12 R12 R11 Gnd Fig. 4. Schematic of circuit \follower". Fig. 5. Placement for circuit \follower", obtained by DLP. time depends almost only on the amount of space allocated to the circuit. As an example, consider circuit \follower", a two-stage singleended di erential biCmos ampli er, shown in Figure 4. A symmetry constraint is de ned with a non- xed vertical axis, with pairs (P1,P2), (N2,N3), (R21,R22), and self-symmetric components N6, Q9 and R11. N6 and N7 must be aligned and have the same relative orientation, and so do Q9 and Q10, as well as R11 and R12. A Max distance constraint is required between R11 and R12, between R21 and R22, and between N2 and N3. Finally, input, bias and supply pins are xed on the left edge of the cell bounding box, while the output pin is xed on the right edge of the cell. DLP produced a placement satisfying all these constraints, shown in Figure 5, in about 8 seconds. If all constraints are turned o , no signi cant di erence in the CPU time can be observed. ment and achieves the goal of a quick placement consistent with all feasible constraints. When overconstraints are detected, the placer provides information about the infeasible ones, and ignores low-priority constraints to enforce correctly the high priority ones. Work is in progress to re ne the use mode for a constraint-correct interactive editing environment, where the user is either prevented from violating geometric constraints, or immediately noti ed when a violation occurs. The starting point for this approach is the on-line interactive DRC check available in some advanced editing environments. 5. Conclusions A new constraint-driven placement tool for full-custom design called DLP has been described in this paper. Through a combination of force-directedplacement, min-cut partitioning, and iterative optimization, it is able to perform the placement of full-custom layout cells subject to large sets of geometric constraints. The six categories of geometric constraints we consider have been de ned, and the techniques used to enforce each of them have been described. The results obtained on a signi cant set of industrial-strength test cases show that this approach produces good quality placeCircuit typea N. comp. CPUb aoi21 D 14 8 amp A 15 4 di Amp A 16 3 fbAmp A 21 9 follower A 21 8 latch D 24 19 xor2 D 15 3 muxes D 35 32 opamp A 17 5 multi D 56 60 Table 1. DLP performance on a sample of M/S circuits. (a) D: Digital cell - A: Analog cell { (b) In sec. on a SUN SPARCstation-5 with 64 MB RAM. References [1] E. Malavasi, E. Charbon, E. Felt and A. Sangiovanni-Vincentelli, \Automation of IC Layout with Analog Constraints", IEEE Trans. on CAD, vol. 15, n. 8, pp. 923{942, August 1996. [2] J. M. Cohn, D. J. Garrod, R. A. Rutenbar and L. R. Carley, Analog Device-Level Layout Automation, Kluwer Academic Publ., Boston, MA, 1994. [3] J. M. Cohn, D. J. Garrod, R. A. Rutenbar and L. R. Carley, \KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing", IEEE Journal of Solid State Circuits, vol. 26, n. 3, pp. 330{342, March 1991. [4] E. Charbon, E. Malavasi, U. Choudhury, A. Casotto and A. Sangiovanni-Vincentelli, \A Constraint-Driven Placement Methodology for Analog Integrated Circuits", in Proc. IEEE CICC, pp. 2821{2824, May 1992. [5] J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, \GORDIAN: VLSI placement by quadratic programming and slicing optimization", IEEE Trans. on CAD, vol. 10, pp. 356{365, 1991. [6] T. H. Altho and F. Johannes, \PLACEBO: Analog Placement",  Hirzel-Verlag, Stuttgart, vol. 49, n. 2, pp. 55{63, 1995. AEU, [7] M. Hanan and J. M. Kurtzberg, \Placement Techniques", in Design Automation of Digital Systems, M. A. Breuer Editor, pp. 213{282, Prentice-Hall Inc., Englewood Cli s, NJ, 1972. [8] C. M. Fiduccia and R. M. Mattheyses, \A Linear Time Heuristic for Improving Network Partitions", in Proc. IEEE/ACM DAC, pp. 175{181, 1982. [9] H. Chang et al., A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, Kluwer Academic Publ., Boston, MA, 1996. [10] S. Sutanthavibul and Shragowitz, \An Adaptive Timing-Driven Layout for High Speed VLSI", in Proc. IEEE/ACM DAC, pp. 90{95, June 1990. [11] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, \Matching Properties of MOS Transistors", IEEE Journal of Solid State Circuits, vol. 24, pp. 1433{1440, October 1989.