A PROJECT REPORT on SUN TRACKING SOLAR SYSTEM USING BUCK BOOST CONVERTER AND WAP Submitted in partial fulfillment for the award of the degree of BACHELOR OF TECHNOLOGY in ELECTRONICS AND COMMUNICATION ENGINEERING by A. P. VIGNESH (10404385) R. SUNIL SURENDER (10404362) R. VASANTHA RAJA (10404377) Under the guidance of Mrs. M. NEELAVENI AMMAL, M.E., (Senior Lecturer, Department of Electronics and Communication Engineering) FACULTY OF ENGINEERING & TECHNOLOGY S.R.M. Nagar, Kattankulathur Kancheepuram District – 603 203 Tamil Nadu MAY 2008 BONAFIDE CERTIFICATE Certified that this project report “SUN TRACKING SOLAR SYSTEM USING BUCK BOOST CONVERTER AND WAP” is the bonafide work of “A. P. VIGNESH (10404385), R. SUNIL SURENDER (10404362) and R. VASANTHA RAJA (10404377)” who carried out the project work under my supervision. HEAD OF THE DEPARTMENT INTERNAL GUIDE INTERNAL EXAMINER EXTERNAL EXAMINER Date: ACKNOWLEDGEMENT We take sincere efforts to acknowledge the guidance and the advice of all the people who have helped us in completing this project successfully. We express our gratitude to Dr. C. MUTHAMIZHCHELVAN, Associate Director (E&T), SRM University and Dr. T. P. GANESAN, Pro Vice Chancellor, SRM University for aiding us in our endeavor to complete the project. We are greatly obliged to Dr. S. MALARVIZHI, Professor and Head, Department of Electronics and Communication Engineering. We express our sincere gratitude to our guide Mrs. M. NEELAVENI AMMAL, Senior Lecturer, Electronics and Communication Engineering. We express our gratitude to our project coordinator Mrs. J. K. KASTHURI BHA, Lecturer, Electronics and Communication Engineering.. We would like to thank our loving parents for their constant support and encouragement. ABSTRACT Normally solar cells are placed in a ground in one direction only. But sun moves in an elliptical path. So only few hours the sunlight falls into the cell. During the rest of the hours the percentage of Sunlight, which falls into the cell, is very less. This results in less amount of energy generation. To overcome this problem we can construct a model where we can place the solar cell in it and which can move in elliptical path To track the sunlight. This is achieved with the help of light intensity sensors. The sensors are fixed into the model in an elliptical path. So depending on the sunlight the sensors output differs. So according to the position of the solar panel, this results in good efficiency. (i.e.).the solar cell can produce energy by tracking the sunlight with the help of sensors and mechanical model. In our project WAP Enabled cell phone is used. The movement of the model can be monitored on the Cell phone by specifying the mobile no through a modem. Also these parameters can be monitored on a remote terminal by specifying the IP address. For this we should have an Internet connection available.WAP stands for Wireless Application Protocol. WAP is an open, global specification that empowers mobile users with wireless devices to easily access and interact with information and services instantly CONTENTS CHAPTER 1. TITLE PAGE NO INTRODUCTION 01 1.1 BLOCK DIAGRAM 02 1.2 CIRCUIT DIAGRAM 03 PIC MICRO CONTROLLER 04 2.1 PIC OVERVIEW 05 2.2 PERIPHERAL FEATURES 06 2.3 MEMORY ORGANISATION 07 2.4 INTERRUPTS CONTROL REGISTERS 12 2.5 POWER SUPPLY 14 3. MAX232 17 4. RS232 19 5. UART 21 5.1 SYSTEM SIGNALS 22 5.2 DMA INTERFACE 22 5.3 SERIAL COMMUNICATION SIGNALS 23 6. LIGHT DEPENDENT RESISTORS 25 7. SOLAR CELL 27 7.1 PRINCIPLE OF SOLAR CELL 32 7.2 APPLICATIONS 34 2. 8. 9. 10. STEPPER MOTOR 36 8.1 TYPES OF STEPPER MOTOR 37 8.2 STEPPER DRIVER 39 8.3 TYPES OF STEPPER DRIVES 41 BUCK BOOST CONVERTER 43 9.1 RINCIPLES OF OPERATIONS 44 9.2 ADVANTAGES 45 WAP 47 10.2 WAP LAYERS 48 10.3 WAP GATE WAY 48 LIST OF DIAGRAMS SL.NO DIAGRAMS PAGE NO 1. BASIC BLOCK DIAGRAM 02 2. CIRCUIT DIAGRAM 03 3. PIC PIN DIAGRAM 05 4. CIRCUIT DIAGRAM OF PIC 07 5. POWER SUPPLY CIRCUIT 15 6. MAX232 PIN DIAGRAM 17 7. CIRCUIT DIAGRAM OF MAX232 18 8. CIRCUIT DIAGRAM OF LDR 25 9. CIRCUIT DIAGRAM OF STEPPER DRIVER 40 ABSTRACT Normally solar cells are placed in a ground in one direction only. But sun moves in an elliptical path. So only few hours the sunlight falls into the cell. During the rest of the hours the percentage of Sunlight, which falls into the cell, is very less. This results in less amount of energy generation. To overcome this problem we can construct a model where we can place the solar cell in it and which can move in elliptical path To track the sunlight. This is achieved with the help of light intensity sensors. The sensors are fixed into the model in an elliptical path. So depending on the sunlight the sensors output differs. So according to the position of the solar panel, this results in good efficiency. (i.e.).the solar cell can produce energy by tracking the sunlight with the help of sensors and mechanical model. In our project WAP Enabled cell phone is used. The movement of the model can be monitored on the Cell phone by specifying the mobile no through a modem. Also these parameters can be monitored on a remote terminal by specifying the IP address. For this we should have an Internet connection available.WAP stands for Wireless Application Protocol. WAP is an open, global specification that empowers mobile users with wireless devices to easily access and interact with information and services instantly CHAPTER 1 INTRODUCTION Mainly our project deals with,how efficiently we are using the solar energy from other cases.our project main theme is to get maximum solar energy by tracking the sun using light senors.The light senors fixedin the kit,absorbs solar energy and compared the panel rotates as to the sensors,which absorbs high energy. The main advantage of our project is tha we are using WAP,so that we can monitor it using wap enabled cell phone. Normally solar cells are placed in a ground in one direction only. But sun moves in an elliptical path. So only few hours the sunlight falls into the cell. During the rest of the hours the percentage of Sunlight, which falls into the cell, is very less. This results in less amount of energy generation. To overcome this problem we can construct a model where we can place the solar cell in it and which can move in elliptical path To track the sunlight. This is achieved with the help of light intensity sensors. The sensors are fixed into the model in an elliptical path. So depending on the sunlight the sensors output differs. So according to the position of the solar panel, this results in good efficiency. (i.e.).the solar cell can produce energy by tracking the sunlight with the help of sensors and mechanical model. In our project WAP Enabled cell phone is used. The movement of the model can be monitored on the Cell phone by specifying the mobile no through a modem. Also these parameters can be monitored on a remote terminal by specifying the IP address. For this we should have an Internet connection available.WAP stands for Wireless Application Protocol. WAP is an open, global specification that empowers mobile users with wireless devices to easily access and interact with information and services instantly 1 1.1 BLOCK DIAGRAM 2 1.2 BASIC CIRCUIT DIAGRAM 3 CHAPTER 2 PIC MICROCONTROLLER INTRODUCTION Today, micro controllers have become an integral of all automatic and semiautomatic machines. Remote controllers, hand-held communication devices, dedicated controllers that use micro controllers, have certainly improved the functional, operational and performance based specifications. Microcontrollers are single-chip microcomputers, more suited for control and automation of machines and processes. Microcontrollers have central processing unit (CPU), memory, I/O units, timers and counters, analog-to-digital converters (ADC), digital-to-analog converters (DAC), serial ports, interrupt logic, oscillator circuitry and many more functional blocks on chip. All these functional blocks on a single Integrated Circuit (IC), results into a reduced size of control board, low power consumption, more reliability and ease of integration within an application design. The usage of micro controllers not only reduces the cost of automation, but also provides more flexibility. PIN DIAGRAM PIC 16F877A is a 40-pin controller. There are pins corresponding to five I/O ports, namely, PORT A, PORT B, PORT C, PORT D and PORT E. Analog inputs to AD converter are AN0 to AN7; and are the alternate functions of PORT A and PORT E. Two pins are for oscillator connections, namely, OSC1 and OSC2. Supply and reference ground pins VDD and VSS, respectively, are in duplicate. Further, functions associated with the parallel slave port and serial communications are the alternate functions of PORT C and PORT D. RB0/INT is the external interrupt pin. 4 PIN DIAGRAM 2.1 PIC OVERVIEW Peripheral interface controllers (PIC) are a family of microcontrollers by Microchip technology. PIC microcontrollers (16C/FXXX series) have attractive features and they are suitable for a wide range of applications. PIC microcontrollers are RISC processors and uses Harvard architecture. It is a newer concept and came out of the requirement to speed-up the processor. Harvard architecture makes use of separate program and data memories. 5 PIC 16F8XX is a family of CMOS 8-bit Flash controllers. Apart from the flash program memory there is a data EEPROM. 2.2 PERIPHERAL FEATURES • • • • • • • • • • • Operating frequency: DC-20 MHz clock input. DC-200 ns instruction cycle. Wide operating voltage range (2.0V – 5.5V). Instruction set – 35 instructions. 14-bit wide instructions, 8-bit wide data path. 13-bit program counter, 8 level stack (13-bit). 8K X 14 words of flash program memory. Up to 368 byte of data memory (RAM). Up to 256 X 8 bytes of EEPROM data memory. Timer0: 8-bit timer/counter with 8-bit prescaler. Timer1: 16-bit timer/counter with prescalar can be incremented during SLEEP through external crystal/clock. • • • • Timer2: 8-bit timer/counter with 8-bit period register, prescalar and post scalar. Two Capture, Compare, PWM (CCP) modules. Synchronous serial port (SSP) with SPI (master mode) and 12C (master/slave). Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9bit address detection. • Parallel slave port (PSP) 8-bit wide, with external RD, WR and CS controls (40/44 pin only). • Brown out detection circuitry for brown out reset (BOR). 6 PIC CIRCUIT DIAGRAM 2.3 MEMORY ORGANISATION There are three blocks in each of PIC16F8XX series devices. The Program memory and Data memory have separate buses so that concurrent access can occur. PROGRAM MEMORY PIC microcontrollers have separate program memory and data memory with separate address and data buses. The flash program memory of 16F877 is 8k and is 14-bit wide. Therefore, to access this 8k memory, 13-bit address is needed and hence the program counter is 13-bit wide. Again after reset, the program counter points to 0000H and the interrupt vector is at 0004H as seen earlier in case of 16C71.0004H is loaded in the program counter automatically if interrupt are enabled. 13- bit program counter of 16F877 can address 8k program memory; however call and goto instructions have 11-bits of address to support branching within a page. 7 Upper two bits come from the PCLATH<4:3> to form 13k effective address. Page select bits must be programmed to make it possible to address a desired program memory page. While executing return instruction, a complete 13-bit address is popped off from the stack and there is a no need to have any more calculations. DATA MEMORY The data memory of 16F877 is of two types, namely, RAM data memory and EEPROM data memory. DATA RAM The data memory of PIC16F877 is divided into 4 banks. And STATUS register bits IRP, RP1and RP0 are used to select any of the banks. Size of each of these 4 banks is 128 bytes. Further, the lower locations in every bank are reserved for SFRs. Then there are general purpose registers implemented as static RAM. Some of the SFRs also appeared in multiple banks. In a broad sense one can classify a different registers as per their functions. There are SFRs port A, port B, port C, port D and port E in bank0-corresponding to the five I/O ports. Associated with this five I/O ports in bank1 there are direction registers, namely, TRISA, TRISB, TRISC, TRISD, TRISE. STATUS registers, file selection register (FSR), PCL, PCLATH, INTCON are mirrored in all the four banks. OPTION_REG register contains the bits corresponding to the prescaling of TMR0, and watchdog timer, timer 0 source edge selection, external interrupt edge selection, PORTB pull-up enable. There are three timer/counters. Timer 0 is an 8-bit timer with 8-bit prescalar. TMR0 is an8-bit timer0 register in bank 0 and mirrored in bank 2. Timer 1 is a 16-bit timer with prescaler. Two SFRs TMR1L (8-bit) and TMR1h (8-bit) from bank 0 from 16-bit timer1. T1CON is the timer1 control register. Timer2 is an 8-bit timer/counter with 8-bit period register, prescaler and postscaler. TMR2 from bank 0 is the timer 2 SFR. T2CON again from bank0 is the timer2 control register. PR2 is the timer 2 period register. Timer2 is an 8-bit timer/counter with 8-bit period register, prescaler and postscaler. TMR2 from bank 0 is the timer 2 SFR. T2CON again from bank0 is the timer2 control register. PR2 is the timer 2 period register. For interrupt operation, 8 apart from INTCON there are peripheral interrupt enable registers PIE1, PIE2 from bank0 and peripheral interrupt register PIR1, PIR2 from bank1. TIMER CONTROL REGISTERS TIMER0 MODULE The Timer0 module timer/counter has the following features: • • • • • 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select• Interrupt on overflow from FFh to 00h Edge select for external clock Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). Timer1 can operate in one of two modes: • • As a Timer As a Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). 9 T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) TIMER1 MODULE bit 7-6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 10 Legend: R = Readable bit; W = Writable bit ;U = Unimplemented bit, read as ‘0’; n = Value at POR; ’1’ = Bit is set; ’0’ = Bit is cleared; x = Bit is unknown. TIMER2 MODULE Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). Timer2 can be shut-off by clearing control bit, TIMER2 MODULE bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 11 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 2.4 INTERRUPTS CONTROL REGISTERS 16F877 supports 14 interrupt sources. There is an external interrupts RB0/INT, PORTB change interrupt, timer 0 overflow interrupt and peripheral interrupts. Peripheral interrupts are corresponding to the parallel slave port, USART, timer1 and timer2 overflows, AD converter, synchronous serial port and CCP1 (capture compare1), CCP2, SSP bus collision and EEPROM write operation interrupt. POWER CONTROL REGISTER (PCON) Power control register contains the flags which can differentiate between the types of reset occurred, namely, power-on-reset, brown-out- reset, a watch dog timer reset and external MCLR reset. Both POR and BOR bits are readable and writeable. POR is the power-on-reset status bit. If this is 1,then it means that no power-on-reset has occurred, and if it is 0, then it means that power-on-reset has occurred. Similarly BOR is the brown-out-reset status bit. If this is 1, then it means that no brown-outreset has occurred and if it is 0, then it means that brown-out-reset has occurred. Other bits of PCON marked with dashed lines are unimplemented and read as “0”. It must be noted that if the configuration bit ‘BODEN’ allow to enable or disable the brown out-reset circuit. 12 INPUT-OUTPUT PORTS PIC 16F877 supports five I/O ports, namely, PORT A, PORT B, PORT C, PORT D, PORT E. PORT A is 6-bit wide and PORT E is 3-bit wide, whereas all remaining ports PORT B, PORT C, PORT D are 8-bit wide. There are data correction registers TRIS A, TRIS B, TRIS C, TRIS D, TRIS E corresponding to these ports, respectively. PORT A PORT A is a 6-bit wide bi-directional port. The I/O direction is decided by the TRIS A register. Clearing a TRIS A bit will make that particular pin as an output. Reading PORT A will read the pin status, whereas writing PORT A will write to the port latch. Write operations are read-modify-write operations. POPRT A pins have alternate functions of analog inputs and V ref. Pin RA4 is multiplexed with timer 0 module clock input TOCKI pin. PORT B PORT B is an 8-bit wide bi-directional port. TRIS B is the corresponding data direction register. Setting TRIS b bit to 1 will configure the corresponding pin as an input. Clearing the bit in TRIS B will make the corresponding pin as an output. PORT B has an interesting feature of having internal weak pull-ups that can be turned on or off in the similar manner as is done in PIC 16C71.Pull-ups are disabled on power-on-reset. Further pull-ups are automatically disconnected if PORT B is configured as an output. PORT B supports one more important feature of PORT B change interrupt, in which a state change on any one or more pins RB& to PR$ will cause an interrupt. PORT C PORT C is an 8-bit wide bi-direction I/O port. TRIS c is the data direction register associated with PORT C. Again setting a bit in TRIS C will make the corresponding PORT C pins as an input. There are other peripheral functions that are multiplexed with PORT C pins. PORT C pins have Schmitt trigger input buffers. PORT D PORT D is an 8-bit wide port with Schmitt trigger input buffers. Individual pins may be configured as input or output by writing in TRIS D. In addition to this, 13 PORT D can be used as an 8-bit parallel slave port. Setting PSPMODE bit in TRIS E can do this. The alternate functions of PORT D pins RD0 to RD7 are PSP0 to PSP7, respectively. PORT E PORT E is 3-bits wide. The alternate functions of PORT E are RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7. These pins have input Schmitt trigger buffers. When TRIS E bit PSPMODE is set, the I/O PORT E serves as control inputs for the parallel slave ports. In this mode, ADCON1 must be configured for the digital I/O and TRISE bits 0,1,2 are set to ensure that the PORT E bits are digital inputs. PORT E pins can also serves as analog inputs AN5, AN6 and AN7. While doing so, these pins must be configured as inputs. Upon power on reset these pins are configured as inputs. 2.5 POWER SUPPLY The power supply consists of • • • • Step down transformer Rectifier unit Filtering unit Voltage regulator 14 CIRCUIT DIAGRAM STEP DOWN TRANSFORMER When AC is applied to the primary winding of the transformer it can neither be step down or up depending on the value of DC needed. In our circuit the transformer of 230V/12-0-12V is used to perform the step down operation where a230C AC appears as 12V Ac across the secondary winding. One alteration or input causes the top of the transformer to be positive and the bottom negative. The next alteration will temporarily cause the reverse. The current rating of the transformer used in our project is 5A. Apart from stepping down AC voltages, it gives isolation between the power source and power supply circuitries. RECTIFIER UNIT In the power supply, rectification is normally achieved by using a solid-state diode. Diode has the property that will let the electron flow easily in one direction at proper biasing condition.As Ac is applied to the diode, electron only flows when the anode and cathode is negative.Reversing the polarity of voltage will not permit electron flow.A commonly used circuit for supplying large amount of DC power is the bridge rectifier, a bridge rectifier of four diodes (4*In4007) are used to achieve the full wave rectification,two diodes will conduct during the negative cycle and the other two will conduct during the positive half cycle, the Dc voltage apperiang across the output terminals of the bridge rectifier will be some what less than 90% of the applied rms value, normally one alteration of the voltage will reverse the polarities opposite 15 ends of the transformer will therefore always be 180 degree out of phase with each other. For a positive half cycle, two diodes are connected to the positive voltage at the top winding and only one diode conducts. At the same time one of the other two diodes conducts for the negative voltage that is applied from the bottom winding due to the forward bias for that diode. FILTERING UNIT Filter circuits, which is usually capacitor acting as an arrester follow the rectifier unit. This capacitor is also called as a decoupling capacitor or a a by passing capacitor,is used not only to short the ripple with frequency of the Dc to appear at the output. A load resistor R! is connected so that a reference to the ground is maintained C1R1 is for by passing ripples. C@R@ is used as a low pass filter that is it passes only low frequency signals and by passes high frequency signals. The load resistor should be 1% to 2.5% of the load. VOLTAGE REGULATOR The voltage regulator play an important role in any power supply unit. The primary purpose of a regulator is to aid the rectifier and filter circuit in providing a constant Dc voltage to the device, power supplies without regulator have an inherent problems of changing Dc voltage values due to variation in the load or due to fluctuations in AAAC linear voltage with a regulator connected to the DC voltage can be maintained with in a close torelant region of the desired output. IC7812 and 7912 is used in this project for providing +5V and -5V Dc supply, next if voltage ‘V’ is applied to appear to clipper using an ideal diode d, the voltage V1 contains only positive pulses. Thus the sine wave converted into a train of positive pulse at interval T. 16 CHAPTER 3 MAX232 CONVERTER The Max232 acts as a buffer driver for the processor. It accepts the standard digital logic values of 0 and 5 volts and convert them to the Rs232 standard f +10 and -10 volts.It also helps to protect the processor from static that may come from people handling the serial port connectors. The MAX232 from Maxim was the first IC which in one package contains the necessary drivers and receivers to adapt the RS-232 signal voltage levels to TTL logic. It became popular, because it just needs one voltage (+5V or +3.3V) and generates the necessary RS-232 voltage levels PIN DIAGRAM: 17 The MAX232 requires 5 external 10uF capacitors.These are used by the internal charge from to create 10 volts and -10 volts. • For the first capacitor,the negative leg goes to ground and the positive leg goes to pin 16. • For the second capacitor,the negative leg goes to 5 volts and the positive leg goes to pin 2. • For the third capacitor,the negative leg goes to pin 3 and the positive leg goes to pin 1. • For the four capacitor,the negative leg goes to pin 5 and the positive leg goes to pin 4. • For the five capacitor,the negative leg goes to pin 6 and the positive leg goes to pin ground. The MAX232 includes two receivers and two transmitter so two serial ports can be used with a single chip. 18 CHAPTER 4 RS232 RS-232 (Recommended Standard - 232) is a telecommunications standard for binary serial communications between devices. It supplies the roadmap for the way devices speak to each other using serial ports. The devices are commonly referred to as a DTE (data terminal equipment) and DCE (data communications equipment); for example, a computer and modem, respectively. RS232 is the most known serial port used in transmitting the data in communication and interface. Even though serial port is harder to program than the parallel port, this is the most effective method in which the data transmission requires less wires that yields to the less cost. The RS232 is the communication line which enables the data transmission by only using three wire links. The three links provides ‘transmit’, ‘receive’ and common ground. The RS232/DB9 is designed to convert TTL level signals into RS232 level signals. This cable allows you to connect a TTL level device, such as the serial port on a Micro-controller, to the serial port of a personal computer. The conversion circuit is housed inside the DB9 connector shell. Power is supplied from the Micro-controller board. The board is based on the Maxim MAX3221CAE interface chip. This chip draws a mere 1mA of current when there are no RS-232 signals connected to the part. 19 With the exception of the DB9 connector and the wire, all parts on this board are surface mounted, and require care during assembly. The mounting of surface mount parts is not difficult, but does require a steady hand. A magnifying glass or other visual aid may be helpful. You also need some electronic paste flux. The ‘transmit’ and ‘receive’ line on this connecter send and receive data between the computers. As the name indicates, the data is transmitted serially. The two pins are TXD & RXD. There are other lines on this port as RTS, CTS, DSR, DTR, and RTS, RI. The ‘1’ and ‘0’ are the data which defines a voltage level of 3V to 25V and -3V to -25V respectively. RS232 DB9 Connector Pinout DB-9M Function Abbreviation Pin #1 Data Carrier Detect CD Pin #2 Receive Data RD or RX or RXD Pin #3 Transmitted Data TD or TX or TXD Pin #4 Data Terminal Ready DTR Pin #5 Signal Ground GND Pin #6 Data Set Ready DSR Pin #7 Request to Send RTS Pin #8 Clear to Send CTS Pin #9 Ring Indicator RI 20 CHAPTER 5 UART The UART_16550 IP is a Universal Asynchronous Receiver Transmitter module fully compatible with the de-facto standard 16550. This is the standard that can be found in most personal computers and for which a lot of software knowledge and programs is available.The UART provides a full-featured transmitter-receiver pair, configurable by software for different speeds, character widths, parity codification, etc. The receiver provides information status with several error indications. Both the transmitter and the receiver can be equipped, if selected at synthesis time, with a 16character First In First Out (FIFO) buffer. If equipped, the software can decide to put the UART in non-FIFO (16450) mode or in FIFO (16550) mode. For designs requiring low area, the module can be implemented with a 1-character buffer instead of the 16byte FIFO. DMA operation is allowed with two output signals that inform the DMA controller about when is new received data available and when the UART is able to accept new data for transmission. Moreover, the module provides an extension to the 16550 standard providing two DMA transfer flags and associated interrupts. 5.2 KEY FEATURES ̇ ̇ ̇ ̇ ̇ ̇ ̇ Fully compatible with industry-standard 16550. Full-featured, software configurable transmission-reception pair. FIFO capability (default 16 words for both transmission and reception). The implementation of the FIFO can be omitted for a smaller area. DMA capability. Modem control signals. Fully synchronous and static design. No clock gating. Simple RTL codification to easy the use with any Verilog synthesizer. 21 • Provided as a communication core plus FIFO modules, to make possible the connection to technology dependent FIFO memories. • • • • Easy connection to microprocessors. Example connection provided for ARM and AVR. Fully tested on Xilinx and Altera FPGAs. High fault coverage for silicon implementations. 5.1 SYSTEM SIGNALS The complete UART circuitry is driven by the rising edge of the clk clock. This clock is not gated at any time.Every UART register is reset by the reset signal. In order to allow for smaller area in standard cell implementations, asynchronous reset technique has been used.The above sentences are valid for all the provided modules. the UART core and the register-based implementation of the FIFO buffers. INTERRUPT SIGNALS The UART provides an interrupt line irq to the microprocessor. This line will rise as soon as an interrupt condition appears for which the interrupt generation has been enabled. It will stay high until the interrupt condition disappears. To reset this condition the microprocessor will have to execute an appropriate read or write operation.Again to provide more flexibility with low area cost, a complementary signal irq_n is also generated. 5.2 DMA INTERFACE Two standard signals are provided together with their complementary versions in order to manage the operation of an external DMA controller.The signal rxrdy is set to its active value when there is new received data that can be read from the UART by the DMA controller to be put in memory. Depending on the DMA mode being used, this signal may be set when there is any new data or it may wait until a trigger level has been reached in the receiver’s FIFO.The signal txrdy is set to its active value when the UART is ready to receive new characters taken from memory by the DMA controller, in order to be sent through txd. Depending on the DMA mode being used, this signal may be set active only when the 22 transmitter FIFO is completely empty or it may be kept active until the transmitter FIFO gets full. 5.3 SERIAL COMMUNICATION SIGNALS The serial input must be connected to the rxd pin and the serial output to the txd pin.The UART implements for the rxd input an antimetastability filter followed by a majority filter. This inserts a delay of three clock cycles in the view of the rxd that the receiver has respect to a direct sampling of rxd. SERIAL DATA REPRESENTATION Throughout this datasheet the term character will appear. This term is commonly used to describe a word of data being transmitted serially. A character can have several possible word lengths, being the possible ones managed by this module 5, 6, 7 or 8 bits. The serial communication line has an idle state of ‘1’. When no data is being communicated the line is held at high logic level (sometimes called mark). The data transmitted through the serial interface (sent through the txd pin and received through the rxd pin) has the following format: ̇ ̇ ̇ ̇ A start bit, always ‘0’, is sent first. 5 to 8 bits of data follow. The least significantbit is sent first. A parity bit may follow the data bits to provide error checking capability. Finally 1 or more stop bits separate this character from the next one.The exact codification used in the line is selected writing to the Line Control Register (LCR). 23 TRANSMISSION The transmission of data is done through the txd pin.The transmitter has a Transmitter Holding Register(THR) to hold the data to be sent. This buffer is written from by microprocessor. The data in the THR is passed to the Transmitter Shift Register (TSR), which is used to serialize the character data bits. During this serialization process, the start, stop and parity bits are added. RECEPTION The serial data comes into the UART through the rxd pin. The Receiver Shift Register (RSR) gets this data and converts it to parallel format. When a complete character has been assembled it is passed to the Receiver Holding Register (RHR), where it is read from the microprocessor. 24 CHAPTER 6 LIGHT DEPENDENT RESISTORS A photoresistor or LDR is an electronic component whose resistance decreases with increasing incident light intensity. It can also be referred to as a light-dependent resistor (LDR), photoconductor, or photocell. LDRs or Light Dependent Resistors are very useful especially in light/dark sensor circuits. Normally the resistance of an LDR is very high, sometimes as high as 1000 000 ohms, but when they are illuminated with light resistance drops dramatically. When the light level is low the resistance of the LDR is high. This prevents current from flowing to the base of the transistors. Consequently the LED does not light. 25 However, when light shines onto the LDR its resistance falls and current flows into the base of the first transistor and then the second transistor. The LED lights. The preset resistor can be turned up or down to increase or decrease resistance, in this way it can make the circuit more or less sensitive. Light dependent resistors have a particular property in that they remember the lighting conditions in which they have been stored. This memory effect can be minimised by storing the LDRs in light prior to use. Light storage reduces equilibrium time to reach steady resistance values. The light falling on the brown zigzag lines on the sensor, causes the resistance of the device to fall. This is known as a negative co-efficient. There are some LDRs that work in the opposite way i.e. their resistance increases with light (called positive co-efficient). 26 CHAPTER 7 SOLAR CELL A solar cell, made from a monocrystalline silicon wafer.A solar cell or photovoltaic cell is a device that converts light energy into electrical energy by the photovoltaic effect. Photovoltaics is the field of technology and research related to the application of solar cells as solar energy. Sometimes the term solar cell is reserved for devices intended specifically to capture energy from sunlight, while the term photovoltaic cell is used when the source is unspecified. The term "photovoltaic" comes from the Greek phos meaning "light", and "voltaic", meaning electrical, from the name of the Italian physicist Volta, after whom the measurement unit volt is named. The term "photo-voltaic" has been in use in English since 1849. Assemblies of cells are used to make solar modules, which may in turn be linked in photovoltaic arrays.Solar cells have many applications. Individual cells are used for powering small devices such as electronic calculators. Photovoltaic arrays generate a form of renewable electricity, particularly useful in situations where electrical power from the grid is unavailable such as in remote area power systems, Earth-orbiting satellites and space probes, remote radiotelephones and water pumping applications. Photovoltaic electricity is also increasingly deployed in grid-tied electrical systems. 27 SIMPLE EXPLANATION • Photons in sunlight hit the solar panel and are absorbed by semiconducting materials, such as silicon. • Electrons (negatively charged) are knocked loose from their atoms, allowing them to flow through the material to produce electricity. The complementary positive charges that are also created (like bubbles) are called holes and flow in the direction opposite of the electrons in a silicon solar panel. • An array of solar panels converts solar energy into a usable amount of direct current (DC) electricity. • • The DC current enters an inverter. The inverter turns DC electricity into 120 or 240-volt AC (alternating current) electricity needed for home appliances. • • • The AC power enters the utility panel in the house. The electricity is then distributed to appliances or lights in the house. The electricity that is not used will be re-routed and used in other facilities 28 BACKGROUND TO PHOTOVOLTAICS Faced with ever-increasing demand, the earth's sources of non-renewable energy are not expected to last long. Among the many contenders vying to replace fossil fuels, photovoltaic solar cells offer many advantages, including needing little maintenance and being relatively "environmentally-friendly"; the major drawback to date has been cost. In order for photovoltaics to be viable for large-scale energy conversion, their efficiency must be improved whilst making them cheaper Equivalent circuit of a solar cell 29 The schematic symbol of a solar cell To understand the electronic behavior of a solar cell, it is useful to create a model which is electrically equivalent, and is based on discrete electrical components whose behavior is well known. An ideal solar cell may be modeled by a current source in parallel with a diode; in practice no solar cell is ideal, so a shunt resistance and a series resistance component are added to the model. The resulting equivalent circuit of a solar cell is shown on the left. Also shown, on the right, is the schematic representation of a solar cell for use in circuit diagrams. CELL CONSTRUCTION The CdTe/CdS solar cell is based around the heterojunction formed between n-type CdS and p-type CdTe. The basic composition of the cell can be seen in the below Figure. 30 CdS/CdTe solar cell The functions of the different layers are as follows: • Glass The solar cell is produced on a substrate of ordinary window glass, because it is transparent, strong and cheap. Typically around 2-4 mm thick, this protects the active layers from the environment, and provides all the device's mechanical strength. The outer face of the pane often has an antireflective coating to enhance its optical properties. • Transparent conducting oxide Usually of tin oxide or indium tin oxide (ITO), this acts as the front contact to the device. It is needed to reduce the series resistance of the device, which would otherwise arise from the thinness of the CdS layer. • Cadmium sulphide The polycrystalline CdS layer is n-type doped (as CdS invariably is), and therefore provides one half of the p-n junction. Being a wide band gap material (Eg ~ 2.4 eV at 300K) it is transparent down to wavelengths of around 515 nm, and so is referred toas the window layer. Below that wavelength, some of the light will still pass through to the CdTe, due the thinness of the CdS layer (~ 100 nm). • Cadmium telluride The CdTe layer is, like the CdS, polycrystalline, but is ptype doped. Its energy gap (1.5 eV) is ideally suited to the solar spectrum, and it has a high absorption coefficient for energies above this value. It acts as an efficient absorber and is used as the p side of the junction. Because it is less 31 highly doped than the CdS, the depletion region is mostly within the CdTe layer. This is therefore the active region of the solar cell, where most of both the carrier generation and collection occur. The thickness of this layer is typically around 10 µm. • Back contact Usually of gold or aluminium, the back contact proves a low resistance electrical connection to the CdTe. P-type CdTe is a notoriously difficult material on which to produce an ohmic contact, and so the junction will inevitably display some Schottky diode (rectifying) characteristics. Due to its high conductivity, the metal layer needs only be a few tens of nanometres in thickness. Since the active layers of the device are those on top of the glass substrate, this construction is referred to as a superstrate configuration. 7.1 PRINCIPLE OF p-n JUNCTION SOLAR CELL In its simplest form, the solar cell consists of a junction formed between ntype and p-type semiconductors, either of the same material (homojunction) or different materials (heterojunction). The bandstructure of the two differently doped sides with respect to their Fermi levels can be seen in Figure. Figure : Band structure of differently-doped semiconductors When the two halves are brought together, the Fermi levels on either side are forced in to coincidence, causing the valence and conduction bands to bend (Figure ). 32 Figure : Heterojunction band-bending These bent bands represent a built-in electric field over what is referred to as the depletion region. When a photon, with an energy greater than the bandgap of the semiconductor, passes through the solar cell, it may be absorbed by the material. This absorption takes the form of a band-to-band electronic transition, so an electon/hole pair is produced. If these carriers can diffuse to the depletion region before they recombine, then they are separated by the electric field, causing one quantum of charge to flow through an external load. This is the origin of the solar cell's photocurrent, and is shown in Figure . 33 Figure : Principle of photovoltaic device 7.2 APPLICATIONS OF CdS/CdTe Currently, the semiconductor most widely used in solar cells is single-crystal silicon. Because of the cost involved in producing the bulk material, cells produced by this method are prohibitively expensive for all but the smallest scale or most specialised applications (such as on calculators and satellites). Higher efficiencies have been produced by using single-crystal III-V semiconductors and more elaborate constructions (e.g. multi-quantum wells), but this advantage has always been more than offset by the resultant increase in cost. The thin-film cadmium telluride / cadmium sulphide solar cell has for several years been considered to be a promising alternative to the more widely used silicon devices. It has several features which make it especially attractive: • The cell is produced from polycrystalline materials and glass, which is a potentially much cheaper construction than bulk silicon. • The chemical and physical properties of the semiconductors are such that the polysilicon thin-films can be deposited using a variety of different techniques . 34 • CdTe has a bandgap which is very close to the theoretically-calculated optimum value for solar cells under unconcentrated AM1.5 sunlight. • CdTe has a high absorption coefficient, so that approximately 99% of the incident light is absorbed by a layer thickness of only 1µm (compared with around 10µm for Si), cutting down the quantity of semiconductor required. A concern often expressed about CdS/CdTe solar cells is the effect on health and the environment of the cadmium used. However, the thinness of the films means that the amount of active material used is relatively small; it has been estimated that even if CdTe solar cells were to provide more than 10% of the world's energy requirements, this would still only account for less than a tenth of the world's cadmium usage. 35 CHAPTER 8 STEPPER MOTOR A stepper motor is an electromechanical Device which converts electrical pulses intodiscrete mechanical movements. The shaftor spindle of a stepper motor rotates in discrete step increments when electrical command pulses are applied to it in the proper sequence. The motors rotation has several direct relationships to these applied input pulses. The sequence of the applied pulses is directly related to the direction of motor shafts rotation. The speed of the motor shafts rotation is directly related to the frequency of the input pulses and the length of rotation is directly related to the number of input pulses applied. A Stepping Motor System consists of three basic elements, often combined with some type of user interface (Host Computer, PLC or Dumb Terminal) In addition, the indexer is typically required to perform many other sophisticated command functions.The Driver (or Amplifier) converts the indexer command signals into the power necessary to energize the motor windings. There are numerous types of drivers, with different current/amperage ratings and construction technology. Not all drivers are suitable to run all motors, so when designing a Motion Control System the driver selection process is critical. The Step Motor is an electromagnetic device that converts digital pulses into mechanical shaft rotation.Advantages of step motors are low cost, high reliability, high torque at low speeds and a simple, rugged construction that operates in almost any environment. The main disadvantages in using a step motor is the resonance effect often exhibited at low speeds and decreasing torque with increasing speed. 36 STEPPING MODES The following are the most common drive modes. • • • • Wave Drive (1 phase on) Full Step Drive (2 phases on) Half Step Drive (1 & 2 phases on) Microstepping (Continuously varying motor currents) 8.1 TYPES OF STEPPER MOTORS There are three basic stepper motor types. They are : • • • Variable-reluctance Permanent-magnet Hybrid They differ in terms of construction based on the use of permanent magnets and/or iron rotors withlaminated steel stators. VARIABLE RELUCTANCE The variable reluctance motor does not use a permanent magnet. As a result, the motor rotor can move without constraint or "detent" torque. This type of construction is good in non industrial applications that o not require a high degree of motor torque, such as the positioning of a micro slide . 37 The variable reluctance motor in the above illustration has four "stator pole sets" (A, B, C,), set 15 degrees apart. Current applied to pole A through the motor winding causes a magnetic attraction that aligns the rotor (tooth) to pole A. Energizing stator pole B causes the rotor to rotate 15 degrees in alignment with pole B. This process will continue with pole C and back to A in a clockwise direction Reversing the procedure (C to A) would result in a counterclockwise rotation. PERMANENT MAGNET The permanent magnet motor, also referred to as a "canstack" motor, has, as the name implies, a permanent magnet rotor. It is a relatively low speed, low torque device with large step angles of either 45 or 90 degrees. It's simple construction and low cost make it an ideal choice for non industrial applications, such as a line printer print wheel positioner. Unlike the other stepping motors, the PM motor rotor has no teeth and is designed to be magnetized at a right angle to it's axis. The above illustration shows a simple, 90 degree PM motor with four phases (A-D). Applying current to each phase in sequence will cause the rotor to rotate by adjusting to the changing magnetic fields. Although it operates at fairly low speed the PM motor has a relatively high torque characteristic. 38 HYBRID Hybrid motors combine the best characteristics of the variable reluctance and permanent magnet motors.They are constructed with multi-toothed stator poles and a permanent magnet rotor. Standard hybrid motors have 200 rotor teeth and rotate at 1.80 step angles. Other hybrid motors are available in 0.9ºand 3.6º step angle configurations. Because they exhibit high static and dynamic torque and run at very high step rates, hybrid motors are used in a wide variety of industrial applications. 8.2 STEPPER DRIVE BASIC STEPPER MOTOR DRIVER OPERATION • The LM555 (IC 1) astable oscillator produces CLOCK pulses that are fed to PIN 11 of the 74194 (IC 2) shift register. • Each time the output of the LM555 timer goes HIGH (positive) the HIGH state at the 74194's OUTPUT terminals, (PIN's 12, 13, 14, 15), is shifted either UP or DOWN by one place. ̇ The direction of the output shifting is controlled by switch S1. When S1 is in the OFF position (centre) the HIGH output state will remain at its last position and the motor will be stopped. ̇ ̇ Switch S1 controls the direction indirectly through transistors Q2 and Q3. When the base of Q2 is LOW the output shifting of IC 2 will be pins 15 - 14 13 - 12 - 15; .etc. ̇ When the base of Q3 is LOW the output shifting of IC 2 will be pins 12 - 13 14 - 15 - 12; .etc. 39 ̇ The direction of the output's shifting determines the direction of the motor's rotation. • The outputs of the 74194 are fed to four sets of paralleled segments of a ULN2803 Darlington driver (IC 3). When an input of a ULN2803 segment is HIGH, its darlington transistor will turn ON and that OUTPUT will conduct current through one of the motors coils. • As the coils of the motor are turned ON in sequence the motor's armature rotates to follow these changes. Refer to following diagram. 40 DRIVER TECHNOLOGY OVERVIEW The stepper motor driver receives low-level signals from the indexer or control system and converts them into electrical (step) pulses to run the motor. One step pulse is required for every step of the motor shaft.In full step mode, with a standard 200 step motor, 200 step pulses are required to complete one revolution. Likewise, in microstepping mode the driver may be required to generate 50,000 or more step pulses per revolution.In standard driver designs this usually requires a lot of expensive circuitry. (AMS is able to provide equal performance at low cost through a technology developed at AMS known as VRMC®; Variable Resolution Microstep Control) Speed and torque performance of the step motor is based on the flow of current from the driver to the motor winding. The factor that inhibits the flow, or limits the time it takes for the current to energize the winding, is known as inductance. The lower the inductance, the faster the current gets to the winding and the better the performance of the motor. To reduce inductance, most types of driver circuits are designed to supply a greater amount of voltage than the motors rated voltage . 8.3 TYPES OF STEP MOTOR DRIVERS For industrial applications there are basically three types of driver technologies. They all utilize a "translator" to convert the step and direction signals from the indexer into electrical pulses to the motor.The essential difference is in the way they energize the motor winding. The circuit that performs this task is known as the "switch set." UNIPOLAR The name unipolar is derived from the fact that current flow is limited to one direction. As such, the switch set of a unipolar drive is fairly simple and inexpensive. The drawback to using a unipolar drive however, is it's limited capability to energize all the windings at any one time. As a result, the number of amp turns (torque) is reduced by nearly 40% compared to other driver technologies. Unipolar drivers are good for applications that operate at relatively low step rates.R/L (resistance/limited) 41 drivers are, by today's standards, old technology but still exist in some (low power) applications because they are simple and inexpensive. The drawback to using R/L drivers is that they rely on a "dropping resistor" to get almost 10 times the amount of motor current rating necessary to maintain a useful increase in speed. This process also produces an excessive amount of heat and must rely on a DC power supply for it's current source. BIPOLAR CHOPPER Bipolar chopper drivers are by far the most widely used drivers for industrial applications. Although they are typically more expensive to design, they offer high performance and high efficiency. Bipolar chopper drivers use an extra set of switching transistors to eliminate the need for two power sources. Additionally, these drivers use a four transistor bridge with recirculating diodes and a sense resistor that maintains a feedback voltage proportional to the motor current. Motor windings, using a bipolar chopper driver, are energized to the full supply level by turning on one set (top and bottom) of the switching transistors. The sense resistor monitors the linear rise in current until the required level is reached. At this point the top switch opens and the current in the motor coil is maintained via the bottom switch and the diode. Current "decay" (lose over time) occurs until a preset position is reached and the process starts over. This "chopping" effect of the supply is what maintains the correct current voltage to the motor at all times. 42 CHAPTER 9 BUCK-BOOST CONVERTER A boost-buck (also known as a Ĉuk) converter is a single-switch converter, which consists of a cascade of a boost converter followed by a buck converter. Two different topologies are called buck-boost converter. • The inverting topology - The output voltage is of the opposite polarity as the input • A Buck (step-down) converter followed by a Boost (step-up) converter - The output voltage is of the same polarity as the input, and can be lower or higher than the input The buck-boost converter is a type of DC-DC converter that has an output voltage magnitude that is either greater than or less than the input voltage magnitude. It is a switch mode power supply with a similar circuit topology to the boost converter and the buck converter. The output voltage is adjustable based on the duty cycle of the switching transistor. One possible drawback of this converter is that the switch does not have a terminal at ground; this complicates the driving circuitry. Also, the polarity of the output voltage is opposite the input voltage. Neither drawback is of any consequence if the power source is isolated from the load circuit (if, for example, the source is a battery) as the source and diode can simply be reversed and the switch moved to the ground side. 43 BUCK-BOOST DC/DC CONVERTER SMALL SIGNAL MODEL (TRANSFER FUNCTION) 9.1 PRINCIPLE OF OPERATION Schematic of a Buck-Boost converter. 44 The two operating states of a buck-boost converter: When the switch is turnedon, the input voltage source supplies current to the inductor and the capacitor supplies current to the resistor (output load). When the switch is opened (providing energy is stored into the inductor), the inductor supplies current to the load via the diode D. The basic principle of the buck-boost converter is fairly simple (see figure ): • while in the On-state, the input voltage source is directly connected to the inductor (L). This result in accumulating energy in L. In this stage, the capacitor supplies energy to the output load; • while in the Off-state, the inductor is connected to the output load and capacitor, so energy is transferred from L to C and R. Compared to the buck and boost converters, the characteristics of the buck- boost converter are mainly: • polarity of the output voltage is opposite to that of the input; • the output voltage can vary continuously from 0 to (for an ideal converter). The output voltage ranges for a buck and a boost converter are respectively 0 to Vi and Vi to .0 9.2 ADVANTAGES AUTOMATIC BOOST AND BUCK OPERATION The converter can both boost and buck the input voltage. Thus, it is ideal for cases where the output LED string voltage can be either above or below the input voltage based on the operating condition. CONTINUOUS INPUT AND OUTPUT CURRENTS The converter has inductors on both the input and output sides. Operating both stages in continuous conduction mode (CCM) will enable continuous currents in both inductors with low current ripple, which would greatly reduce the filter capacitor requirements at both input and output. Continuous input current would also help greatly in meeting conducted EMI standards at the input. 45 LOCALIZED SWITCHING All the switching nodes in the circuit are isolated between the two inductors. The input and output nodes are relatively quiet. This will minimize the radiated EMI from the converter and with proper layout and design the converter can easily meet radiated EMI standards. FAILURE OF THE SWITCHING FET One of the advantages of the boost-buck converter is the capacitive isolation. The failure of the switching transistor will short the input and not affect the output. Thus, the LEDs are protected from failure of the FET. 46 CHAPTER 10 WIRELESS APPLICATION PROTOCOL Wireless Application Protocol (WAP) is an open international standard for applications that use wireless communication. Its main use is to enable access to the Internet from a mobile phone or PDA. A WAP browser provides all of the basic services of a computer based web browser but simplified to operate within the restrictions of a mobile phone, such as its smaller view screen. WAP sites are websites written in, or dynamically converted to, WML (Wireless Markup Language) and accessed via the WAP browser. Before the introduction of WAP, service providers had extremely limited opportunities to offer interactive data services. Interactive data applications are required to support now commonplace activities such as: • Email by mobile phone • Tracking of stock market prices • Sports results • News headlines • Music downloads WHAT IS WAP WAP (Wireless Application Protocol) is a protocol that makes it possible to surf the Internet from a cellular phone or other handheld wireless devices. Many of us that surf the Internet from home with a 56kbps modem thinks that is slow and a cell phone only uses 9.6kbps so WAP have to take the lesser bandwidth into consideration. Some other disadvantages are the small display that a web page has to fit into, in the cell phone, and the few buttons to interact with. It's not possible to achieve a HTML page directly to the cell phone, it wouldn't fit and the download time should be too long and costly. 47 10.1 WAP LAYERS The WAP architecture follows the OSI layering model and consists of five layers but I will only, discuss the three top most layers here. These layers are the Application Layer (WAE), the Sessio Layer (WSP) and the Transaction Layer (WTP) (protocols abbreviations in parenthesis). 10.2 WAP GATEWAY The WAP Forum solves the problems with the small display and the narrow bandwidth by introducing a gateway between the cell phone and the WWW server. The cell phone can't communicate with a WWW server directly but instead it goes through a gateway that decodes the requests from the cell phone and encodes the answers to the cell phone. The gateway talks to the WWW server and delivers the answer to the cell phone. The language the micro browsers in the cell phones understand is WML (Wireless Markup Language) so the gateway's job is to translate the HTML response from the web server to a WML response and send the answer to the phone.WML is pretty similar to HTML but with many restrictions because of the limited display and bandwidth.By using a WAP gateway instead of communicating with a WAP server directly increases the usability though all pages in HTML-format can be accessed without being converted to WML-format. The pages is being converted in the gateway but the responsible people for the web server doesn't need to write all the HTML pages in WML format also. This will probably speed the deployment and industry-acceptance of WAP. 48 REFERENCES www.electronicforyou.com www.howstuffswork.com www.solarbuzz.com www.siliconlabs.com www.freepatentsonline.com 49