See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/4133911 Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models Conference Paper · April 2005 DOI: 10.1109/ISQED.2005.81 · Source: IEEE Xplore CITATIONS READS 14 156 4 authors, including: Yuanzhong Zhou Duane Connerney 64 PUBLICATIONS 217 CITATIONS 4 PUBLICATIONS 16 CITATIONS Analog Devices, Inc. SEE PROFILE Fairchild Semiconductor SEE PROFILE All content following this page was uploaded by Yuanzhong Zhou on 11 June 2015. The user has requested enhancement of the downloaded file. All in-text references underlined in blue are added to the original document and are linked to publications on ResearchGate, letting you access and read them immediately. Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk Fairchild Semiconductor, South Portland, ME 04106 Paul.Zhou@fairchildsemi.com Abstract A novel macro model approach for modeling ESD MOS snapback is introduced. The macro model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. No external current source, which is essential in most publicly reported macro models, is included since both BSIM3vs and VBIC have formulations built in to model the relevant effects. The simplicity of the presented macro model makes behavior languages, such as Verilog_A, and special ESD equations not necessary in model implementation. This offers advantages of high simulation speed, wider availability, and less convergence issues. Measurement and simulation of the new approach indicates that good silicon correlation can be achieved. 1. Introduction ESD (Electro-Static Discharge) is a major reliability concern for IC chip manufacturing. It is well known that ESD failures constitute a major portion of customer returns [1]. On-chip ESD protection is needed to protect IC chips against ESD damages. However, ESD protection circuitry interacts with I/O buffers and core circuits. ESD protection structures can have adverse impact on core product functions and product cost due to ESD-induced parasitic effects and silicon consumption. On the other hand, I/O buffers and core circuitry can also impact ESD protection performance. It is important to have effective optimization method in ESD protection circuit design. Currently, trial-and-error approaches still dominate in ESD design, which result resource-consuming iteration. Integrated simulation for ESD and core function circuits is gaining significant importance as the complexity of modern IC is increasing. SPICE modeling that can be incorporated into electronic circuit simulation is very useful to assure both ESD protection and core circuitry work properly and to reduce iteration in circuit design. ESD protection devices and other devices under ESD stress are operated in unconventional manners, such as high operation voltage and large electrical current. The main tool used by circuit designers is SPICE. Conventional compact SPICE models are not optimized for ESD modeling. Many important effects for ESD are not modeled at all or modeled insufficiently. MOSFET transistors in snapback operation mode, i.e. ground gate NMOS (ggNMOS) and gate couple NMOS (gcNMOS), are widely used as ESD protection in CMOS technology. The parasitic lateral bipolar transistor that intrinsically exists in the MOS transistor (Drain=Collector, Substrate=Base, Source=Emitter), as well as its Collector/Base breakdown effect, is the key to snapback-based MOS ESD protection circuitry. BSIM3 is the most widely used MOS model. BSIM3, like most other SPICE MOS models, does not include the lateral parasitic bipolar transistor and the junction breakdown effect [2]. Therefore, regular MOSFET models alone are not suitable for ESD snapback simulation. Numerical SPICE modeling efforts on snapback-based MOS ESD simulation have been publicly reported (for example, [3]-[8]). The reported macro or subcircuit models normally extend main MOS with three additional components: a BJT, a current source and a substrate resistor. These models usually need special SPICE implementations, which may limit the availability of the models and may have disadvantages on simulation speed and convergence. A new approach that provides simple SPICE macro models for the snapback of MOS ESD protection devices is presented in this paper. The macro model is constructed from standard circuit elements only. The device models for those standard circuit elements can be found in most commercial circuit simulation tools. It makes the SPICE simulation for ESD protection more accessible to ESD and I/O circuit designers. 2. Snapback and SPICE Models The MOS transistor behavior under standard operating conditions, as well as under ESD stress, is well known after many excellent investigations[1]. The I-V characteristic of a typical NMOS with different gate bias is schematically shown in Figure 1. The I-V curve consists essentially of four regions. Region (1) and (2) are the Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05) 0-7695-2301-3/05 $ 20.00 IEEE linear and the saturation regions respectively. The characteristic in Region (1) and (2) is exclusively determined by the NMOS behavior and is modeled well by standard MOS equations in regular SPICE models. Region (3) is the avalanche breakdown region and is influenced both by the MOSFET and the parasitic NPN bipolar transistor. The standard MOS equations are no longer adequate in this region. Region (4) is the highcurrent characteristic or snapback region, which is dominated by the parasitic NPN bipolar transistor. The NMOS transistor operates in Region (1) and (2) under normal conditions. It goes to Region (3) and (4) under ESD stress. Further increasing Vd will lead to secondary snapback, which is not shown in the figure. for substrate resistance. The NPN is usually modeled with EM (Ebers-Moll) or GP (Gummel-Poon) equations. The impact ionization current in NMOS and/or avalanche current in BJT are modeled by a current source Igen. The current source is an essential component and is modeled as [9] Igen = (M − 1) ⋅ (I ds + I c ) (1) D Id=Ids+Ic+Igen Ic Igen Ib G Ids Region (4) Region (2) Isub Id Rsub Region (3) Region (1) Gate Bias S Figure 2: Basic Subcircuit of ESD Compact Model Vd Figure 1: Schematic I-V curve of an NMOS transistor under gate bias showing operation regions As the drain voltage Vd increases from 0V, the drainsubstrate junction is reverse-biased. Once Vd reaches the avalanche region, the electrical field in the depletion layer becomes high enough that many electron-hole pairs are generated by impact ionizations. The electrons flow to the drain, becoming part of the drain current. The holes are injected into the substrate, causing rise of the substrate current Isub. As Isub increases, the voltage drop across the substrate resistance (Vbe for the lateral bipolar transistor) increases and eventually the source-substrate junction becomes forward biased, causing electrons emitted into the substrate from the source. When Vbe reaches ~0.5V, the lateral bipolar transistor turns on and the electron current reaching the drain further increases the generated electron-hole pairs. Since a high electrical field is no longer needed to maintain the current level through impact ionization alone, the drain voltage decreases and snapback happens. The modeling accuracy of the voltage drop across the substrate resistance is critical since it determine when snapback occurs. The snapback effect is basically modeled with the subcircuit shown in Figure 2. It consists of a NMOS, a parasitical NPN, an explicit current source, and a resistor where M is the multiplication fact, Ids is the MOS surface drain current, and Ic is the BJT collector current. The multiplication fact M, as well as the gain of the current source (M-1), is not a constant. M is a function of the drain voltage and the MOS saturation voltage. It is often given by “Miller formula” [3]: M = 1 K2 § · 1 − K 1 ⋅ exp ¨ − ¸ − V d V dsat © ¹ (2) where K1, K2 are fitting parameters related to drain depletion width and impact ionization coefficients. The gate voltage dependence of M is included through Vdsat. The equation may cause convergence problem if it is directly implemented in circuit simulators. As Vd increases, the denominator can go to zero, which results a discontinuity in M. The substrate resistance has been shown, by experiment data, to not be a constant either. To address this effect, the resistor is replaced with a dynamic substrate resistance, modeled by a current controlled voltage source Vsub [10] V sub = R sub ⋅ Isub − R d ⋅ (I d − Ids ) (3) The equation (3) decouples the substrate current model from the MOS model. There are some other versions, such as using two current sources for Igen [8], adding a second avalanche Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05) 0-7695-2301-3/05 $ 20.00 IEEE current source to the source-substrate junction [6]. However, all variations basically are similar to the circuit in Figure 2 and include NMOS, BJT, current source and resistors. Special setups in CAD are needed to implement current source and/or substrate resistance. The models have to be implemented either as a new SPICE model in CAD simulators by EDA vendors [3], or using behavior languages Verilog-A or VHDL-A [4][5]. Using behavior languages could significantly lower simulation speed and sometimes may cause convergence problems. And both implementations may have limited availability and be difficult for many circuit designers to access. 3. New Subcircuit Using BSIM3 and VBIC The subcircuit we present is shown in Figure 3. In this subcircuit, all elements are standard SPICE devices and there are no explicit external current or voltage sources. The NMOS is modeled with BSIM3V3 and the BJT with VBIC model. Vd D Id=Ids+Ic Rd Ic Ids G Ib Isub VBIC BSIM3v3 Isub_total Rsub Rs S Figure 3: New subcircuit for ESD snapback simulation Here, we take the advantage of the substrate current modeling in BSIM3 and the collector base avalanche modeling in VBIC. The substrate current in BSIM3 model is given by [2] § α0 Isub = ¨¨ α 1 + Leff © · ¸¸ ⋅ (Vds − Vdeff ¹ )⋅ e § β0 ¨¨ − © Vds − Vdeff · ¸¸ Idsa ¹ (4) where Idsa is the drain current without considering of impact ionization, Leff is the effective channel length of the MOS, Vdseff becomes Vdsat in the saturation region, and Į0, Į1 and ȕ0 are fitting parameters. The gate voltage dependence of the multiplication fact, resulted from the gate coupling between the MOS and the parasitic BJT, is included in the equation. The avalanche current of the collector-base junction in the VBIC model is equivalently given by: ( MC −1) Iave = Ic ⋅ AVC1 ⋅ (PC − Vbci) ⋅ e − AVC2⋅( PC −Vbci ) (5) where Ic is the collector current without avalanche, PC represents the junction built-in potential, MC is the junction grading coefficient, Vbci the voltage drop over the junction, AVC1 and AVC2 are fitting parameters [11]. Equivalently, the subcircuit in Figure 3 has two parallel avalanche current sources between the drain and the substrate, like in [8]. The two avalanche current equations have similar exponential voltage dependence. This property offers several modeling advantages. First, with two parallel current sources, the substrate current model is at least partially decoupled from the intrinsic MOS model. Second, there are more fitting parameters to work with than using a single current source, which offers modeling engineers more control on the substrate current to achieve accurate voltage drop across the substrate resistance. Third, it overcomes the discontinuity problem that exists in equation (2) and has similar computational stability as that offered by the new multiplication factor formulations in [6] and [12]. On the other hand, lacking external current and voltage sources makes CAD implementation of the macro model much simpler. The major drawback of most publicly reported models is that their implementation in CAD is not straightforward, as we discussed in the previous section. To create the model structure shown in Figure 3 one only needs to connect the standard component devices together. The model even can be run standalone without the need of expensive full suite simulation CAD platforms. BSIM3v3 and VBIC models are included widely in commercial circuit simulators. The algorithms for both BSIM3v3 and VBIC have been fine-tuned in their implementation. Therefore, convergence problems much less likely happen in simulation. The simulation is faster without Verilog-A or VHDL-A being part of the modeling solution. BSIM3v3 and VBIC have sophisticated capacitance modeling. This makes our macro model suitable not only quasi-static process modeling but also simulation for transient events. Additionally, VBIC can bring some other advanced features to the macro ESD model. VBIC has simulation capability for self-heating effect. In the version 1.3 update, base-emitter breakdown modeling has been added to VBIC [13]. Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05) 0-7695-2301-3/05 $ 20.00 IEEE 4. Model Validation by Measurement The model has been tested with actual silicon devices. In model extraction, the BSIM3v3 model for NMOS and the VBIC model for BJT are extracted first using regular methodology respectively, with emphasis on substrate current and overlap capacitance. Then the substrate resistance, Rsub, was extracted from the snapback curves from ggNMOS structures measured with TLP. We found that sometimes it is necessary to make minor tweaks on some BJT model parameters to fit measured snapback curves. When a MOS device is under normal operating condition, the BJT should have insignificant impact on device behavior. Figure 4 shows the simulation comparison of Id-Vd curves using the ESD macro model and the NMOS alone model respectively. The difference is negligible. The Id in the ESD model is slightly higher, which is caused by the small positive bulk potential due to the substrate resistor. 0.25 The substrate current plays a critical role in ESD modeling. Figure 5 is the substrate currents vs. the drain voltage Vd for several different gate voltages. The substrate currents under low Vgs start higher at low Vd but end lower at high Vd than the substrate currents under high Vgs. The simulation curves fit the measured data very well. Snapback phenomenon is the central part of NMOS ESD protection. It is usually measured with transmission line pulse (TLP) technique. Through TLP measurement is mostly regarded as a quasistatic event, it does have a transient effect on trigger voltage Vt1 when capacitance coupling becomes significant. We developed a program to simulate the snapback effect using a pulse sequence as the input. The snapback simulation has been run with both DC and pulse inputs. Figure 6 shows the snapback data of a grounded gate NMOS device. The simulation data fitted the measured curve very well. 1.8 0.35 0.3 Vg=5V 0.2 1.44 0.25 0.15 1.08 0.2 Id (A) (%) Vg=4V Id (A) Vg=3V 0.1 0.72 0.05 0.36 0.15 0.1 0.05 Vg=2V 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 2 3 4 5 6 7 8 9 10 Vd (V) Vd (V) Figure 4: Simulation comparison of the ESD (solid line) and MOS alone (dash line) models under normal operation conditions. The dotted line is the difference Figure 6: Snapback curves of a ggNMOS structure (lines: simulation, symbols: measurement) 0.4 -2 10 0.35 Vg=1.05 V -4 10 0.3 -6 0.25 10 Vg=0.75 V Id (A) Ib (A) 0.2 -8 10 Vg=3.0 V 0.15 Trise=8.0ns -10 10 0.1 Vg=2.0 V 0.05 -12 10 Trise=1.5ns 1 1.5 2 2.5 3 3.5 4 4.5 5 0 Vd (V) 3 3.5 4 4.5 5 5.5 6 6.5 Vd (V) Figure 5: Simulation (lines) and measurement (symbols) substrate currents as function of Vd and Vg Figure 7: Snapback curves of a NMOS w/ a gate resistor (lines: simulation, symbols: measurement) Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05) 0-7695-2301-3/05 $ 20.00 IEEE Figure 7 shows the snapback data of a NMOS transistor with a 10K resistor between its gate and the ground. The data demonstrate that Vt1 decreases as the edge time of the input pulses is reduced. The physical reason behind this phenomenon is the gate voltage raise resulted from the coupling between the gate and the drain through the overlap capacitance is. The extracted models have been applied to ESD protection blocks to test the capability of predicting ESD trigger voltage Vt1, using voltage pulses as the input. The rising and fall edge was 8ns, same as in the pulses used in the measurement. The simulation predicted Vt1=6.8V for an output protection circuit which was a modified gate coupling NMOS structure. The results correlated perfectly with the measured Vt1=6.7V from silicon. modeling capability. The results show that most current flows through the pulldown device NOUT, instead of the ESD production devices. 2.5 2 Current through output NMOS 1.5 I (A) 1 0.5 5. HBM Simulation Examples Current goes to ESD protection 0 0 HBM simulation have been run on individual NMOS devices and whole circuits with integrated ESD protection, I/O buffers, and core function circuitry. The circuits used in the simulation have ESD protection blocks between the input pad and the ground, between the output pad and the ground, and between the VCC pad and the ground. 25 20 Regular MOS model alone 15 Vg (V) ESD Snapback model 10 5 0 0 20 40 60 80 100 120 140 160 180 200 T (ns) Figure 8: Simulated gate voltages of the input buffer during a HBM event across the pad pair of input and ground using regular and ESD models The simulation of the HBM test over the input and ground shows that the ESD snapback model predicts the gate voltage clamp on the input buffer while the regular NMOS model does not (Figure 8). In the ESD model simulation, current flows through the ESD block to the ground. The simulation results of the HBM test over the output and ground is shown in Figure 9. In the simulation, both the NMOS for ESD protection (NESD) and the NMOS in output buffer for pulldown (NOUT) have snapback 20 40 60 80 100 120 140 160 180 200 T (ns) Figure 9: Simulated current distribution during a HBM event across the pad pair of output and ground Snapback competition can exist between the NESD and NOUT. Through NOUT usually has higher Vt1 than NESD under same operation conditions (for ggNMOS structure, it is 9.0V vs. 10.8V in this example), the operational conditions in an actual integrated circuit can be more favorable to one or another. The voltage monitor in the simulation revealed that the gate voltage of NOUT is about 100~900 mV higher than the gate voltage of NESD during the HBM event. The higher gate voltage makes snapback triggers in the NOUT device before the ESD protection block reaches its own Vt1. A simulation using the regular NMOS model for the NOUT has been done for comparison. The results indicated that almost all the current goes through the ESD protection block. This implies that snapback modeling is not only needed in the ESD protection transistors but also in the NOUT transistor as well as any other MOS transistors that may have ESD stress across their drain and source during ESD shock events. 6. Conclusion A new macro model approach for modeling ESD MOS snapback is presented in this paper. The macro model structure takes the advantage of the built-in formulas and fine-tuned algorithms in sophisticated BSIM3v3 and VBIC models. It consists of standard components only and has no external current source. The simplicity of the model makes behavior languages, such as Verilog_A, and special ESD equations unnecessary in the model implementation. This offers advantages of high simulation speed, wider availability, and less convergence issues. It also has the advantage of separate equations for impact Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05) 0-7695-2301-3/05 $ 20.00 IEEE ionization current in NMOS and avalanche current in BJT to offer more modeling control. The simulation of models from the new approach has been correlated to measurement data. HBM stress simulation has been carried out and demonstrated that this new simple modeling approach can significantly enhance the effectiveness integrated SPICE simulation for ESD, I/O buffers and core circuitry. 7. Acknowledgements The authors wish to acknowledge Mr. Jay Chapin for his helpful discussions. 8. Reference Strong Impact Ionization in sub-0.25um NMOS Devices", IEDM 97 (1997), p.885-888. [11] C. McAndrew, etc., "VBIC95, The Vertical Bipolar Inter-Company Model", IEEE J. Solid State Circuits, Vol.31, No.10, p.1476-1482, 1996 [12] S. L. Lim, X. Y. Zhang, Z. Yu, S. Beebe, and R. W. Dutton, "A Computational Stable Quasi-Empirical Compact Model for the Simulation of MOS Breakdown in ESD-Protection Circuit Design", Proc. SISPAD (1997), p.161-164. [13] C. McAndrew, T. Bettinger, L. Lemaitre, and M. Tutt, "BJT Modeling with VBIC, Basics and V1.3 Updates", Workshop of Compact Model (2003), p.278-281. [1] A. Amerasekera, C. Duvvury, “ESD in Silicon Integrated Circuits”, Second Edition, John Wiley, Chichester, England, 2002. [2] Y. Cheng and C. Hu, “MOSFET Modeling & BSIM3 User’s Guide”, Kluwer Academic, Boston, USA, 1999. [3] A. Amerasekera, S. Ramaswamy, M. C. Chang M, and C. Duvvury, "Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulations", Proc. IRPS (1996), p.318. [4] X. F. Gao, J. J. Liou, J. Bernier, G. Croft, and A. Ortiz-Conde, "Implementation of a Comprehensive and Robust MOSFET Model in Cadence SPICE for ESD Applications", IEEE Trans- CAD, v. 21, p.1497, 2002. [5] J. Li, S. Joshi, E. Rosenbaum, “A Verilog-A Compact Model for ESD Protection NMOSTs”, Proc. Custom Integrated Circuits Conference (2003), p.253. [6] M. Mergens, W. Wilkening, S. Mettler, Wolf H., Fichtner W., "Modular Approach of a High Current MOS Compact Model for Circuit-level ESD Simulation Including Transient Gate-coupling Behavior", Proc. IRPS (1999), p.167. [7] T. Li, C.-H. Tsai, E. Rosenbaum, and S.-M. Kang, "Substrate Resistance Modeling and Circuit-level Simulation of Parasitic Device Coupling Effects for CMOS I/O Circuits under ESD Stress," Proc. 20th EOS/ESD Symp. (1998), p.281. [8] H. Anzai, Y. Tosaka, K. Suzuki, T. Nomura and S. Satoh, "Equivalent Circuit Model of ESD Protection Devices", Fujitsu Sci. Tech. J., vol. 39, p. 119-127, 2003. [9] F. Hsu, P. Ko, S. Tam, and R. Miller, "An Analytical Breakdown Model for Short-Channel MOSFET’s", IEEE Trans. Elec. Dev., ED-29, p.1835-1740, 1982. [10] S. Ramaswamy, A. Amerasekera, and M-C. Chang, "A Unified Substrate Current Model for Weak and Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05) 0-7695-2301-3/05 $ 20.00 IEEE