Timing Closure

2001

Abstract Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation, logic synthesis and layout synthesis are iterated until the estimates match. The number of such iterations is becoming larger as technology scales. Timing closure problems occur mainly due to the difficulty in accurately predicting interconnect delay during logic synthesis.

2001

Proceedings of the tenth international workshop on System level interconnect prediction - SLIP '08, 2008

Proceedings of the 41st annual conference on Design automation - DAC '04, 2004

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017

Variations in integrated circuits stem from multiple sources. This paper studies variations in placement and delay that occur when using commercial EDA in a relatively unsupported fashion – to implement large unclocked circuits. A tool suite is built to study placed and routed designs. Significant variations in physical placement is shown, leading to degradation in performance, power efficiency, and robustness. An experimental method of mitigating timing and placement variation using relative place directives is applied, resulting in circuits that are 7% faster and 4% lower power.

Proceedings of the 2002 international symposium on Physical design, 2002

intechopen.com

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

In Deep Sub Micron (DSM) technologies, circuits fail to meet the timings estimated during synthesis after completion of the layout which is termed as ‘Timing Closure’ problem. This work focuses on the study of reasons for failure of timing closure for a given synthesis solution. It was found that this failure is due to non-adherence of synthesizer’s assumptions during placement. A synthesis aware new placer called ANUPLACE was developed which adheres to assumptions made during synthesis. The new algorithms developed are illustrated with an example. ANUPLACE was applied to a set of standard placement benchmark circuits. There was an average improvement of 53.7% in the Half-Perimeter-Wire-Lengths (HPWL) with an average area penalty of 12.6% of the placed circuits when compared to the results obtained by the existing placement algorithms reported in the literature.

2006