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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 9, SEPTEMBER 2011
An Optimized Implementation of Phase Locked
Loops for Grid Applications
Francisco D. Freijedo, Member, IEEE, Alejandro G. Yepes, Student Member, IEEE, Óscar López, Member, IEEE,
Pablo Fernández-Comesaña, Student Member, IEEE, and Jesús Doval-Gandoy, Member, IEEE
Abstract—This paper presents an optimized digital implementation of phase locked loops (PLLs) for grid applications suitable
for implementation in low-cost industrial devices. A robust PLL
is crucial in most of power converter applications, particularly in
distorted environments. That is, the phase estimation should not
be affected by power quality phenomena, given by Standard EN
50160, such as harmonics, imbalance, line notching, and voltage
sags. The PLL dynamics is optimized as follows. A notch filter
inside the loop is implemented to enhance the steady-state filtering.
The bandwidth is maximized to get a fast postfault retracking
(transient response). As justified in this paper, this approach
is very suitable for both single- and three-phase PLLs. A lowresource-consuming implementation of the digitally controlled
oscillator is provided: A digital model based on an RC electronic
oscillator implements the needed trigonometric functions. This
reduces the needed digital resources without reducing the performance. The proposed PLLs have been implemented and tested in a
fixed-point DSP TI TMS320LF2407. These PLLs have been tested
using different distorted inputs. Experimental results show that
fast and rippleless phase estimations are achieved by the proposed
implementations.
Index Terms—AC/DC power conversion, dc/ac power conversion, phase estimation, phase locked loops (PLLs), power electronics converters.
I. I NTRODUCTION
S
YNCHRONIZATION is one of the most important issues
in the control of power electronics equipment connected to
the grid [1], [2]. Most of the power converter control algorithms
use the phase measurement of the grid voltage fundamental
component. A quick and accurate phase estimation allows for
a good generation of reference signals, so the performance of
the power converter is enhanced [3]. Examples of applications
where synchronization is necessary are active power filters
[4], power factor control [5], grid monitoring in distributed
power generation systems [6], flexible ac transmission systems
[7], etc.
Manuscript received September 16, 2010; revised November 3, 2010;
accepted November 6, 2010. Date of publication March 28, 2011; date of
current version August 10, 2011. This work was supported in part by the
Spanish Ministry of Science and Innovation and in part by the European
Commission (Fonds Européen de Développement Régional) under project
number DPI2009-07004. The Associate Editor coordinating the review process
for this paper was Dr. Alessandro Ferrero.
The authors are with the Department of Electronics Technology, Superior Technical School of Industrial Engineering, University of Vigo, 36310
Vigo, Spain (e-mail: fdfrei@uvigo.es; agyepes@uvigo.es; olopez@uvigo.es;
pablofercom@uvigo.es; jdoval@uvigo.es).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2011.2122550
Phase locked loops (PLLs) tracking the phase of the fundamental component of grid voltages are the most widespread
synchronization algorithms for both single- and three-phase
systems [2], [3], [8]–[11]. PLLs are implemented inside a
higher level control; they should be designed with the goals of
having a good performance and not being excessively resource
consuming. This paper presents a PLL design method for an
optimized digital implementation in low-cost industrial devices.
This approach is suitable for both single- and three-phase
systems.
PLLs with a good tradeoff between the transient response
and harmonic/noise cancellation are presented. Notch filters
inside the loop to cancel second-harmonic components are
implemented with this goal. This proposal is very useful for
both single- and three-phase PLLs. Single-phase PLLs generate
a high second harmonic in the phase-detector (PD) output (e.g.,
a multiplier) [9], [10]; the notch filter cancels it in an effective
way. The problem of second-harmonic generation in threephase PLLs appears when the input voltages are unbalanced [3],
[12]. A linear control approach has been carried out to optimize
the bandwidth without compromising stability.
The major novelty of this paper is the implementation of
the digital oscillator to implement trigonometric functions:
The input of the digitally controlled oscillator (DCO) is the
PLL output frequency, and a digital oscillator is derived from
an analog RC one. The oscillation conditions are imposed
by means of the Barkhausen criteria [13]. From the point of
view of digital implementation in low-cost DSPs and fieldprogrammable gate arrays (FPGAs) (fixed-point devices), this
is a very good solution in terms of resource consumption and
design simplicity.
The performance of the proposed PLLs is proved experimentally. The PLLs have been implemented in a fixed-point
DSP. For the experimental tests, different input waves have been
programmed using a programmable ac source. Tests include
waveforms with grid faults, imbalance, harmonics, and ac-line
notching.
II. PLL S FOR G RID A PPLICATIONS
A PLL is a nonlinear circuit or algorithm which synchronizes
its output signal vo with a reference or input signal vi in
frequency and phase. In steady state, the mean value of the
error signal ve should be zero, which means locked state [14]. In
locked state, the input fundamental frequency ωi and phase θi
equal the output frequency ωo and phase θo , respectively. The
basic PLL scheme is composed of the three basic functional
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FREIJEDO et al.: AN OPTIMIZED IMPLEMENTATION OF PHASE LOCKED LOOPS FOR GRID APPLICATIONS
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is an important advantage over other digital techniques,
such as stochastic and finite-impulse response filters [19].
A. State-of-the-Art Review
Fig. 1.
Block diagram of a generic PLL.
blocks shown in Fig. 1: the PD, the loop filter (LF), and the
voltage-controlled oscillator (VCO) or DCO. The VCO/DCO
generates a signal of frequency ωo from its nominal frequency
ωn and a “correction” voltage vc . When a proportional–integral
(PI) filter is used as LF, this PLL achieves a zero steadystate error even after a phase jump or a frequency step in the
reference input [14].
Focusing on grid-connected power converter applications,
the main role of PLLs is to synchronize with the grid voltage fundamental component. Moreover, in detail, an accurate
phase-angle estimation is crucial in the control of energy flows
and power factor. The main metrological characteristics of
grid voltages are available in Standard EN 50160 [15] and
summarized as follows.
1) In normal operation conditions, the input voltage magnitude is very limited, e.g., Standard EN 50160 gives
acceptable variations of ±10% of the nominal magnitude
during 95% of a week.
2) Power frequency is very limited and should not oscillate
so much around the nominal value, e.g., Standard EN
50160 limits frequency deviations in 1% of the nominal
value (50 or 60 Hz) during 99.5% of a week in an
interconnected system. This limit is wider in isolated
systems.
3) AC mains may be distorted with voltage harmonics and
imbalance. Standard EN 50160 gives acceptable limits for
steady-state distortion, e.g., the total harmonic distortion
(THD) should be lower than 8%.
4) Occasionally, the grid voltage magnitude can be suddenly
reduced below 90% (of nominal magnitude) and recovered after a short period of time. These grid faults are
known as sags or dips [15]. Usually, voltage sags are
associated with a significant phase jump [16].
PLLs are specially suitable to track grid voltages because of
the following facts.
1) PLL algorithms are suitable for both single- and threephase applications. Usually, in three-phase applications,
synchronization is made with the fundamental positivesequence component. These PLLs, based on Park’s transformations, are usually known as dq-PLLs [17].
2) Although PLL dynamics depends on the voltage magnitude, industrial equipment limits normal ranges of operation, e.g., the Spanish Grid Code allows to disconnect a
wind farm park from ac mains if the voltage magnitude
remains below 80% of the nominal value during more
than 1 s [18].
3) PLLs are able to provide a zero steady-state phase error,
defined as θe = θi − θo , in the presence of grid frequency
deviations [3], [14]. Good frequency adaptation of PLLs
The state of the art in grid synchronization is wide and
increasing nowadays mainly due to the suitability of digital
implementation [19]. Focusing on PLLs, quite a lot of schemes
have been proposed to optimize their dynamic response.
1) Single-Phase PLLs: The suitability of digital implementation allows to implement PDs better than the first analog
charge pumps [20]. From PLL theory [14], the “linear multiplier” PD seems to be the most simple option but generates
a high-magnitude second harmonic which should be canceled
[1], [9]. Other more complex PDs have been also proposed to
avoid this problem [21]–[23]. Another alternative is to adapt a
dq-PLL by delaying the input wave 90◦ [2], [24], [25]. Singlephase PLLs have a modest transient response due to the second
harmonic generation or the 90◦ delaying filters. Their typical
settling times are not lower than one cycle of ωn , which can be
checked in the referred works.
2) dq-PLLs: The dq-PLL algorithm is suitable to track the
fundamental positive-sequence voltage, instead of individual
phase voltages [3], [8], [17]. This is achieved by means of
Park’s transformation Tdq
vd
vα
cos(θo ) sin(θo )
·
=
(1)
vq
vβ
− sin(θo ) cos(θo )
where
vα
vβ
2
=
3
1
0
−0.5
√
3
2
−0.5
√
− 23
va
· vb .
vc
(2)
The field of application of dq-PLLs is very wide, and hence,
its optimization has been approached in several works [1], [3],
[11], [26]–[28]. A very interesting feature of the dq-PLL is
the absence of second harmonic when there is no fundamental negative sequence (imbalance). Hence, on the contrary to
single-phase PLLs, a dq-PLL can be tuned with a very high
bandwidth, which implies almost instantaneous retracking (after a transient) [3], [8]. However, in the case of distorted
conditions, such as imbalance (second harmonic in vd ) and harmonics, the bandwidth should be reduced drastically [3], [11].
Single-Phase PLLs Against dq-PLLs: Single-phase PLLs
synchronize per phase, but dq-PLLs track a positive-sequence
vector. Therefore, dq-PLLs are more suitable for applications
based on symmetrical components (e.g., power converters implementing dq current controllers [29]), and single-phase PLLs
are better for single-phase applications or three-phase applications with a per-phase controller. The key is the ability to
provide a zero steady-state phase error in the reference frame
of the power converter controller [19].
B. LF Design
Although PLLs are nonlinear, their dynamics can be accurately studied by linear models, obtained assuming a
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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 9, SEPTEMBER 2011
Fig. 2. PLL linearized model.
quasi-locked state: ωi = ωo and θi ≈ θo . Fig. 2 shows the linear
PLL, where H(s) [H(z) for discrete models] means the open
loop transfer function, which is useful to set the dynamics
[1], [3], [8], [14]. H(z) frequency response diagrams give
information about harmonic attenuation, transient response, and
stability margins. Assuming that the DCO/VCO behaves as a
simple integrator [3], [14], the dynamics mainly depends on
the LF. In general, there is a tradeoff between the filtering and
transient response: High-bandwidth PLLs are faster, but their
outputs are more affected by noise and harmonics.
A simple but effective technique includes discrete filtering
to enhance harmonic filtering [1]. In this case, the LF H(z) is
formed by a term dependent on the input amplitude and PD, a
PI controller (lead/lag controllers lose frequency adaptation [3],
[19]), a DCO/VCO integrator, and a harmonic filter
H(z) =
· C(z) ·
N (z)
K|vif |
amplitude gain PI filter harmonic filter
·
Ts
. (3)
z−1
DCO integrator
It should be noted that H(z) also depends on the input
fundamental magnitude vif , which is an uncontrolled parameter.
For this reason, the PLL bandwidth decreases in the presence
of voltage sags [1], [9]. Furthermore, the value of K (constant)
in (3) depends on the PD, e.g., K = 1/2 in the single-phase
PLL with a multiplier PD and K = 1 in the dq-PLL [1]. It is
recommended to adapt the acquired input signals to per unit,
so vif = 1 p.u. at nominal voltage. This makes easier the LF
design [1], [9].
III. D IGITAL I MPLEMENTATION
Digital control is a clear trend in power electronics. Vendors
have developed specific low-cost DSPs for motor control and
other power converter applications, such as the C2000 family
of Texas Instruments [30]. Most of these devices, which are
equipped with specific blocks such as pulsewidth modulation
(PWM) units and A/D converters, have a limited set of instructions and implement fixed-point arithmetic. Hence, implementation techniques which combine structural simplicity, low
resource consumption, and good performance are of paramount
interest [31].
Focusing on digital PLLs, this paper proposes easy modifications to optimize the digital implementation in low-cost
Fig. 3. Key figures of the implemented DCO. (a) DCO block diagram.
(b) Pole/zero map of the DCO (in radians per second) continuous model.
devices, such as fixed-point DSPs and FPGAs. Optimum word
length is analyzed by simulation in order to achieve a good
tradeoff between transient response and quantification errors,
i.e., between speed range and accuracy [32]. It is also shown
that good filtering can be achieved with low-order digital filtering (notch filters) and without making complex the PLL structure. A high-performance DCO implementation is provided
to compute trigonometric functions in a simple but effective
manner.
A. DCO Implementation by Means of an Oscillator Model
PLLs implement trigonometric functions to generate feedback waves cos(θo ) or sin(θo ). The dq-PLLs require both
sin(θo ) and cos(θo ) to generate Park’s matrices.
An efficient algorithm is proposed in the following to achieve
sin(θo ) and cos(θo ). It is based on a digital implementation of
an RC electronic oscillator. Fig. 3(a) shows the model of the
proposed digital oscillator. Fig. 3(b) shows the DCO closedloop poles for ωo = ωn = 2π50 rad/s. Following Barkhausen
criteria, this system oscillates at ωo and tends to instability
since its poles are on the imaginary axis. However, as the
integrators are saturated, the signal amplitude can be controlled.
A nonzero initial value at the output of one of the integrators
(e.g., sin(θo ) = 0 and cos(θo ) = 0.99) is necessary to start the
oscillation [13]. The DCO output phase θo is calculated by
FREIJEDO et al.: AN OPTIMIZED IMPLEMENTATION OF PHASE LOCKED LOOPS FOR GRID APPLICATIONS
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TABLE I
O PTIMUM a VALUES AND THD AS F UNCTION OF fs /fo
means of ωo integration. When sin(θo ) crosses zero in the rising
edge, θo is reset to zero.
The following piece of code stresses the simplicity of the
proposed implementation.
% wo is the DCO frequency
Mysin(n + 1) = Mysin(n) + wo ∗ T s ∗ (Mycos(n));
%(Q15)
Mycos(n + 1) = Mycos(n) − wo ∗ T s ∗ (Mysin(n));
%(Q15)
% Limit the oscillator integrators
Mysin(n + 1) = max([Mysin(n + 1) − 0.99]);
Mysin(n + 1) = min([Mysin(n + 1)0.99]);
Mycos(n + 1) = max([Mycos(n + 1) − 0.99]);
Mycos(n + 1) = min([Mycos(n + 1)0.99]);
% Update the output phase (Q12)
theta(n + 1) = theta(n) + wo ∗ T s;
% Output phase reset condition
if Mysin(n) >= 0 && Mysin(n + 1) <= 0
theta(n + 1) = −pi;
end
It can be appreciated that this diagram is very low resource
consuming. The drawback of the oscillator model is that the
generated waves sin(θo ) and cos(θo t) are not pure sinusoidal
waveforms due to the nonlinearities. The THD of these waves
depends on the ratio of sampling frequency fs to oscillation
frequency fo (= ωo /2π): Low ratios provide low THD values
and vice versa. Furthermore, the optimum value at which the
integrators should be saturated ±a also depends on it: a should
be chosen so that sin(θo ) and cos(θo t) magnitudes are 1 p.u.
Table I shows the THD and optimum a values for different
fs /fo ratios.
IV. E XAMPLES OF D ESIGN
Some PLL algorithms have been developed to be implemented in a fixed-point device and tested in real time. The
design methodology and other details are explained in the
following.
A. Single-Phase PLL for 50-Hz Grid
Fig. 4 shows a single-phase-PLL 16-b fixed-point implementation designed for 50-Hz grids (ωn = 2π50 rad/s). Its
main routine involves 13 multiplications and 9 additions. The
DCO (Fig. 3(a) and code below) is implemented with three
additions and five multiplications. Following the guidelines
in Section II-B, the LF has been designed. The PLL can be
linearized, assuming quasi-locked state, resulting in the model
in Fig. 2[1]. The K = 1/2 term introduced by the PD multiplier
Fig. 4. Block diagram of the proposed single-phase PLL.
Fig. 5. Bode diagram of H(z). (Solid line) |vif | = 1 p.u. (Dotted line)
|vif | = 0.5 p.u. During a 0.5-p.u. voltage sag, fc drops from 37 to 20 Hz (PM
slightly increases to 57◦ ).
is compensated inside the loop. A notch filter with a notch
peak at 2ωn is placed to cancel the second harmonic. Finally,
by inspection of Bode diagrams, the PI filter coefficients are
chosen. Equation (3) can be particularized as
H1 (z) =
250z − 249 0.972z 2 − 1.9402z + 0.972
·
z−1
z 2 − 1.9402z + 0.944
PI controller
notch filter Q=0.8
·
0.0001
· 2
. (4)
z−1
gain comp
DCO
Fig. 5 shows the H1 (z) frequency response in nominal
conditions, i.e., considering vif = 1 p.u. It can be noted that
100-Hz components are totally canceled in steady state. The
postfault settling time ts can be quite accurately estimated from
the cutoff frequency fc and phase margin (PM) by a linear
control design relation [33]
ts ≈
100
.
P M · fc
(5)
It should be also noted that the loss of gain in the presence
of a voltage sag results in a slower transient response. A
zoomed inspection around the notch peak permits to estimate
the filtering performance in the presence of grid frequency
deviations: In this case, the H1 (z) values are approximately
−40 and −30 dB when the fundamental frequency shifts ±1
and ±2 Hz. The actual effect of the high second harmonic in
the PLL has been tested in Section V-A.
Fig. 4 shows word lengths of the LF path in Q format for
16 b. Usually, the word length should be adjusted to minimize
quantification errors but keeping good transient response [32].
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Fig. 6. Influence of word length in transient response in the single-phase PLL
discussed in Section IV-A.
Fig. 8. Phase measurement θo for a sinusoidal input of 51.5 Hz: Zero crossing
corresponds with θo = 0, and θo = 0 is rippleless. Scales: vi and cos(θo ) in
0.5 p.u./div and time in 2.5 ms/div.
Fig. 7. Block diagram of the dq-PLL.
In this example, the bottleneck is at the PI controller output. The
word length was optimized by Matlab simulation scripts [1].
Fig. 6 shows the error signal ve (PI controller input) during a
initial transient with θe = 90◦ for different word length values.
The Q9 word length was chosen because its “settling time” is
similar to the Q8 one.
B. dq-PLL for Distorted 60-Hz Grid
Fig. 7 shows the block diagram of a dq-PLL implemented for
a 60-Hz grid (Park’s matrices are generated with the proposed
DCO). Its main routine involves 15 multiplications and 11
additions (only vd is calculated). The direct component vd is
controlled within a closed loop, so its mean value in steady
state is zero, which results in fundamental positive-sequence
tracking. The system is considered near locked state to set
the dynamics (the 1/2 term in the PD does not appear in the
dq-PLL) [3], [8].
A notch filter with a notch peak at 2ωn is placed to cancel the
effect of the fundamental negative sequence. In this example, it
has been recalculated to be at 120 Hz. The same PI controller
in Section IV-A has been implemented. This leads to approximately the same fc as in the single-phase PLL but a slightly
higher PM (≈60◦ ), so from (5), the settling time is slightly
improved. It should be noted that the limited bandwidth of this
dq-PLL also provides a good rejection to other kinds of steadystate disturbances such as harmonics and ac-line notching.
C. dq-PLL in 400-Hz Grid
Frequencies as high as 400 Hz are used in some applications
such as aircraft, submarines, and military equipment. A dq-PLL
for 400-Hz grid applications is designed in the following,
assuming that the input is balanced. The sampling frequency
should be increased to have a low THD at the DCO outputs,
as shown in Section III-A(fs = 50 kHz). The PI controller has
been recalculated so fc ≈ 500 Hz.
V. E XPERIMENTAL R ESULTS
The proposed PLL algorithms have been implemented in a
16-b fixed-point DSP of Texas Instruments TMS320LF2407.
This DSP was embedded in a MSK2407 board of Technosoft,
which also includes A/D and D/A converters. The average
execution times of each implementation were approximately
10 µs. An external programmable ac source has been employed
to generate the input waves. The experimental tests have been
designed to show the real performance of the PLLs in the
presence of main voltage disturbances described in the Standard
EN 50160 [15]. The main criteria to assess the quality of PLL
estimation are the presence/absence of ripple (above all, of
second harmonic) and of the error signal ve (input of the PI
controller) to achieve zero (average value) after a grid fault [1],
[3], [9].
A. Single-Phase PLL in 50-Hz Grid
The implementation example in Section IV-A has been
tested, and key figures are depicted and discussed in the
following.
1) Frequency Deviation Test: As previously discussed, a
PLL should keep the performance in the presence of grid
frequency deviations: A zero average phase error and good
filtering in steady state are expected. From Section II-B, the two
poles at the origin assure perfect tracking. The filtering is more
critical since the notch peak does not correspond with nominal
conditions. Experimental tests gave good frequency adaptation.
Fig. 8 shows a capture by the single-phase PLL with a clean
FREIJEDO et al.: AN OPTIMIZED IMPLEMENTATION OF PHASE LOCKED LOOPS FOR GRID APPLICATIONS
Fig. 9. Phase measurement θo for a distorted input: Rippleless estimation.
Scales: vi and cos(θo ) in 0.5 p.u./div and time in 2.5 ms/div.
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Fig. 11. Phase measurement for unbalanced and notched three-phase input
signal of nominal frequency 60 Hz: Rippleless estimation. Scales: va , vb , and
vc in 0.5 p.u./div and time in 5 ms/div.
time necessary to cancel the error (phase retracking). According
to (5) and Fig. 5, it takes about a cycle.
B. dq-PLL for Distorted 60-Hz Grids
Fig. 10. Voltage sag (in vi ) from 1 to 0.5 p.u. and −45◦ phase-angle jump.
Phase error ve is canceled in around a cycle. Scales: vi , cos(θo ), and ve in
0.5 p.u./div and time in 5 ms/div.
input wave oscillating at a very deviated frequency. The phaseangle estimation of θo is rippleless, and zero crossing of the
(clean) input wave corresponds with θo = 0.
2) Harmonic Distortion: The single-phase PLL has been
tested in the presence of high-magnitude voltage harmonics in
the input wave. From Fig. 5, good rejection of harmonics is
expected. Fig. 9 shows experimental results proving that θo is
rippleless.
3) Transient Response: Grid faults such as voltage sags are
usually associated with phase-angle jumps [16]. When implemented as part of a power converter controller, a PLL should
retrack as fast as possible in the presence of grid faults. Fig. 10
shows the transient response of the analyzed PLL in the presence of a voltage sag with a phase jump. The error signal ve (the
input of the PI controller) is depicted to better appreciate the
This section shows the results of the implementation example
explained in Section IV-B.
1) Filtering of Imbalance and AC-Line Notching: As said,
voltage imbalance due to the fundamental negative sequence
generates a second harmonic ripple in vd [3]. On the other hand,
ac-line notching mainly causes high-frequency components in
vd [8]. As previously discussed, the dq-PLL in Section IV-B
should filter these effects. Fig. 11 shows the results when the
fundamental negative-sequence amplitude is around 1/4 of the
positive sequence and deep notches over the ac signals are also
programmed. It is shown that the obtained phase estimation
is rippleless. It should be noted that θo does not (necessarily)
coincide with va zero crossing since a dq-PLL corresponds with
the positive sequence, not with individual phase voltages, as
explained in Section II-A3.
2) Transient Response: The dq-PLL should retrack fast in
the presence of voltage sags with phase jumps, e.g., grid codes
for wind turbine applications require a fast acting control in the
presence of voltage sags of amplitude below a certain threshold
[18]. Fig. 12 shows the transient response of the analyzed PLL
in the presence of a strong voltage sag with a phase jump. The
error signal ve (the input of the PI controller) is depicted to
better appreciate the phase retracking. This result confirms the
expected performance (Section IV-B) of the system.
C. dq-PLL for 400-Hz Grids
Finally, the dq-PLL for a 400-Hz grid is tested under nominal
and ideal conditions. As discussed in Section IV-C, the sampling frequency has been increased up to 50 kHz in order to
have an acceptable THD in the DCO outputs. Fig. 13 proves
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ployed to identify the error signal spectra. It should be noted
that these error signal spectra do not depend on simulation
initial conditions (e.g., relative phase of harmonics) since the
steady-state dynamics of PLLs is almost linear (Section II-B).
The main error sources, included in the models, are enumerated
in the following:
1) the truncation in digital filters due to fixed-point dynamics [34];
2) the white noise due to the 12-b A/D conversion [35];
3) the noise of the DCO outputs (nonzero THD in Table I);
4) grid frequency deviations (the notch zero is fixed, so
filtering worsens);
5) harmonics, imbalance, and noise (ac-line notching) of the
input voltage.
Fig. 12. Voltage sag in va , vb , and vc : From 1 to 0.5 p.u. and −45◦ phaseangle jump. Phase error ve is canceled in around a cycle. Scales: va , vb , and vc
in 0.5 p.u./div and time in 5 ms/div.
It could be noted that other sources of error, such as the A/D
conversion and computational times, have not been included.
This is because the digital control design methodology for
power converters should include these effects: Due to sampling
effects and computational and PWM delays, digital controllers
work with at least one sample delay, which should be included
in the whole control modeling [31]. Oscilloscope errors have
been also neglected (not relevant in a digital controller).
A. Effect of Grid Frequency Deviation in Single-Phase PLL
As discussed in Section V-A1, the main source of error
tends to be the second harmonic due to the fact that the input
frequency is deviated. Table II shows accuracy as function
of the frequency deviation. The accuracy of the measurement
shown in Fig. 8 is highlighted in Table II.
B. Effect of Grid Harmonics in the Single-Phase PLL
Fig. 13. Phase measurement for 400-Hz three-phase input signal: Rippleless
estimation. Scales: va , vb , and vc in 0.5 p.u./div and time in 500 µs/div.
the good steady-state performance (rippleless estimation) of the
implementation.
VI. P ERFORMANCE E VALUATION BY S IMULATION
Computational techniques are widely employed to study the
dynamics of nonlinear systems like PLLs. By modeling and
simulating a PLL, it is possible to assess in a quick and accurate
way several features for which an analytical study would be
very cumbersome and even inaccurate [14], [20].
The experimental tests performed in the previous section
have been emulated by Matlab/Simulink models, like the one
in Fig. 14, to estimate the (steady-state) accuracy of the phase
measurements. In each case, the tolerance has been assessed
from the worst case scenario, i.e., by adding the magnitudes
of the error signal spectrum. Fig. 15 shows the fast Fourier
transform (FFT) tool of Matlab/Simulink, which has been em-
Table III shows the effect of each harmonic, individually
assessed, by considering an amplitude of 0.1 p.u. for harmonics
and 1 p.u. for the fundamental component. It should be noted
that an input harmonic results in two different components
(different frequencies) after the PD, so in the case of a third
input harmonic, the generated second harmonic is canceled
by the notch filter. Apart from this special case, the accuracy
grows with the harmonic order, as expected from the frequency
response of H1 (z) (at high frequencies, the magnitude gain
decreases 20 dB/decade). Focusing on the input wave in Fig. 9,
it contains 0.1-p.u. amplitude components of third and fifth
harmonics, so the accuracy of the fundamental phase estimation
is ±1.32◦ . The highlighted value in Table III corresponds with
the data in Fig. 15.
C. Voltage Imbalance in the 60-Hz dq-PLL
As said, the effect of imbalance in a dq-PLL is a second
harmonic in the loop for which the amplitude is the fundamental
negative-sequence one. Hence, its effect is also very dependent
on grid frequency deviations. Table IV shows the tolerance due
to a 0.1-p.u. fundamental negative sequence, with 1 p.u. being
the amplitude of the fundamental positive sequence.
FREIJEDO et al.: AN OPTIMIZED IMPLEMENTATION OF PHASE LOCKED LOOPS FOR GRID APPLICATIONS
3117
Fig. 14. Example of a Matlab/Simulink model employed to assess the accuracy of a PLL phase measurement.
Fig. 15. Capture of the Matlab/Simulink FFT tool employed to assess the accuracy of PLL phase measurement. The error signal (signal to analyze) is in radians.
The FFT magnitudes are relative to the base value of 0.01 rad.
TABLE II
ACCURACY AS F UNCTION OF F REQUENCY D EVIATION
TABLE III
ACCURACY FOR E ACH 0.1-p.u. A MPLITUDE I NPUT H ARMONIC
TABLE IV
ACCURACY OF A 0.1-p.u. F UNDAMENTAL N EGATIVE S EQUENCE AS
F UNCTION OF THE F REQUENCY D EVIATION
D. Effect of AC-Line Notching
From the point of view of a frequency spectrum, the ac-line
notching gives rise mainly to high-frequency components, so
good filtering is easily achieved. For example, the accuracy of
the estimation in Fig. 11, which also includes the effect of the
fundamental negative sequence, is ±0.12◦ .
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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 9, SEPTEMBER 2011
E. 400-Hz dq-PLL
The nonlinear effects of the A/D converter and DCO are
higher as the fo /fs ratio decreases. In the case of the estimation
in Fig. 13, the accuracy is ±0.08◦ .
VII. C ONCLUSION
A novel approach in digital implementation of PLLs for grid
applications has been presented in this paper. The proposed
methodology mainly focuses on industrial devices such as lowcost DSPs. By placing a notch filter inside the loop, a good
tradeoff between steady-state filtering and postfault transient
response is achieved. A linear control approach based on inspection of Bode diagrams has been carried out to optimize the
bandwidth and PM. Subsequently, a low-resource-consuming
DCO has been proposed to optimize the implementation of
trigonometric functions. Based on these approaches, a singlephase PLL and a three-phase PLL have been implemented and
tested under realistic conditions. Their good performance has
been proved: rippleless phase estimations and fast transient
responses are obtained. Finally, a simulation-based accuracy
evaluation analysis has been included.
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Francisco D. Freijedo (M’07) received the M.Sc.
degree in physics from the University of Santiago de
Compostela, Santiago de Compostela, Spain, in 2002
and the Ph.D. degree from the University of Vigo,
Vigo, Spain, in 2009.
Since 2005, he has been a Lecturer with the Department of Electronics Technology, Superior Technical School of Industrial Engineering, University of
Vigo. His research interests include the areas of ac
power switching converter technology.
FREIJEDO et al.: AN OPTIMIZED IMPLEMENTATION OF PHASE LOCKED LOOPS FOR GRID APPLICATIONS
3119
Alejandro G. Yepes (S’09) received the M.Sc. degree from the University of Vigo, Vigo, Spain, in
2009, where he is currently working toward the Ph.D.
degree in the Department of Electronics Technology,
Superior Technical School of Industrial Engineering.
Since 2008, he has been with the Department of
Electronics Technology, Superior Technical School
of Industrial Engineering, University of Vigo. His research interests include switching power converters,
grid-connected converters, control of ac drives, and
power quality problems.
Pablo Fernández-Comesaña (S’09) received the
M.Sc. degree from the University of Vigo, Vigo,
Spain, in 2007, where he is currently working toward
the Ph.D. degree in the Department of Electronics
Technology, Superior Technical School of Industrial
Engineering.
Since 2007, he has been with the Department of
Electronics Technology, Superior Technical School
of Industrial Engineering, University of Vigo. His research interests include switching power converters,
grid-connected converters, flexible ac transmission
systems, and power quality problems.
Óscar López (M’05) received the M.Sc. and Ph.D.
degrees from the University of Vigo, Vigo, Spain, in
2001 and 2009, respectively.
Since 2004, he has been an Assistant Professor
with the Department of Electronics Technology, Superior Technical School of Industrial Engineering,
University of Vigo. His research interests include the
areas of ac power switching converter technology.
Jesús Doval-Gandoy (M’99) received the M.Sc.
degree from the Polytechnic University of Madrid,
Madrid, Spain, in 1991 and the Ph.D. degree from
the University of Vigo, Vigo, Spain, in 1999.
From 1991 to 1994, he worked at the industry. He
is currently an Associate Professor with the University of Vigo. His research interests include the areas
of ac power conversion.