Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations of the FPGA, but changing configurations incurs reprogramming costs. The fundamental question for FPGA testing is how to... more
Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations of the FPGA, but changing configurations incurs reprogramming costs. The fundamental question for FPGA testing is how to determine the minimum number of test configurations and corresponding test vector sequences that will cover all the faults for a given FPGA's fault model. In this paper first two types of fault that can occur in the LUT of a FPGA i.e. data faults and addressing faults have been described. Based on this new fault model it has been shown that only 4 configurations are needed for testing of LUTs in a FPGA. A hierarchical approach is then proposed to solve the problem of controllability and observability while testing entire FPGA. This hierarchical approach is faster compared to the other approaches in literature for FPGA testing. The proposed hierarchical approach is also independent of the fault model and configuration used.
