Embedded systems rely on chip to chip communi-cations for exchange of data to be processed. Communication protocols between chips are complex and verification becomes consuming which leaves time and effort for the system designers. In... more
Embedded systems rely on chip to chip communi-cations for exchange of data to be processed. Communication protocols between chips are complex and verification becomes consuming which leaves time and effort for the system designers. In addition, 32-bit microcontrollers and serial eeprom are gaining popularity as they are very suitable for high end processing and data storage. Furthermore, chip to chip communication has to be tailored and optimized to meet the demands of wide range applications. They pose significant challenges to the system designer. In this paper, we present a design methodology needed for chip to chip communication via microwire bus communication protocol interface that combines design and verification together to make it work and operate. A 32bit DSP-RISC based microcontroller and a serial eeprom chip is used to validate the microwire bus communication protocol scheme proposed in this paper. The modeling framework consists of hardware interfacing and software design steps formalized as finite state machines. Circuit design, software algorithm and different set of experimental test are presented in this work. The protocol is implemented and experiment shows data communication between chips without detectable error. The results are satisfactory for both hardware and software level hierarchy and proved the effectiveness of the proposed method. The benefits achieved from this development can be used to aid the system designer for generic chips used to implement the microwire bus communication protocol and verify their correctness.
