Nonvolatile Memories

Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

This dissertation improves the consistency and durability guarantees that file systems can efficiently provide, both by allowing each application to choose appropriate trade-offs between consistency and performance and by dramatically lowering the overheads of durability and consistency using new hardware and careful file system design.

We first describe a new abstraction, the patch, which represents a write to persistent storage and its ordering requirements. This abstraction allows file system modules to specify ordering guarantees without simultaneously requesting more expensive, immediate durability. Algorithmic and data structure optimizations make this abstraction practical, and our patch-based file system implementation is performance-competitive with similarly reliable Linux ext2 and ext3 configurations. To illustrate the benefits of patchgroups, an application-accessible version of patches, we apply them to improve the performance of the UW IMAP server by over 13 times and to make file handling in gzip robust to crashes.

In the second part of this work we investigate using upcoming byte-addressable, persistent memory technologies – in particular, phase change memory – in place of disks and flash to reduce the costs of enforcing ordering constraints and providing durability and atomicity. We describe a new file system, BPFS, that commits each file system operation synchronously and atomically. BPFS exploits byte-addressability, improved throughput and latency, and our new atomic write primitive to eliminate copy-on-writes that have until now been required to implement shadow paging. Our evaluation shows that, because of our optimizations, BPFS provides its exceptionally stronger guarantees on phase change memory without lowering the throughput that today’s file systems achieve on disks.

Solid State Drives (SSDs) using flash memory storage technology present a promising storage solution for data-intensive applications due to their low latency, high bandwidth, and low power consumption compared to traditional hard disk drives. SSDs achieve these desirable characteristics using internal parallelism—parallel access to multiple internal flash memory chips—and a Flash Translation Layer (FTL) that determines where data is stored on those chips so that they do not wear out prematurely. Unfortunately, current state-of-the-art cache-based FTLs like the Demand-based Flash Translation Layer (DFTL) do not allow IO schedulers to take full advantage of internal parallelism because they impose a tight coupling between the logical-to-physical address translation and the data access. In this work, we propose an innovative IO scheduling policy called Parallel-DFTL that works with the DFTL to break the coupled address translation operations from data accesses. Parallel-DFTL schedules address translation and data access operations separately , allowing the SSD to use its flash access channel resources concurrently and fully for both types of operations. We present a performance model of FTL schemes that predicts the benefit of Parallel-DFTL against DFTL. We implemented our approach in an SSD simulator using real SSD device parameters, and used trace-driven simulation to evaluate its efficacy. Parallel-DFTL improved overall performance by up to 32% for the real IO workloads we tested, and up to two orders of magnitude for our synthetic test workloads. It is also found that Parallel-DFTL is able to achieve reasonable performance with a very small cache size.

Nonvolatile Memories (NVMs) can undergo different types of disturbances. These disturbances are particular to the technology and the cell structure of the memory element. In this paper we develop a coupling fault model that appropriately models disturbances in flash memories that use floating gate transistor as their core memory element. We describe the behavior of faulty cells under different fault models and how their characteristics change under each model. We demonstrate the inappropriateness of conventional march algorithms for testing flash memories and present a procedure to derive pseudo-algorithms that can be used in testing flash memories. In addition we present an efficient test that detects these disturbances under different fault models developed in this paper

As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, and easily realize the Runtime Reconfiguration (RTR) and multicontext configuration. However, the conventional MRAM technology based on the Field Induced Magnetic Switching (FIMS) writing approach consumes very high power, large circuit surfaces, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM’s further development in memory and logic circuit. Thermally Assisted Switching (TAS)-based MRAM is then evaluated to address these issues. In this article, some design techniques, novel computing architecture, and logic components for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology and a complete TAS-MTJ spice ...

Chemical vapor deposition based graphene grown on copper foil is attractive for electronic applications owing to its reliable growth process, large area coverage, and relatively defect free nature. However, transfer of the synthesized graphene to host substrate for subsequent device fabrication is extremely sensitive and can impact ultimate performance. Although ultra-high mobility is graphene's most prominent feature, problems with high contact resistance have severely limited its true potential. Therefore, we report a simple poly-(methyl methacrylate) based transfer process without post-annealing to achieve specific contact resistivity of 3.8 × 10−5 Ω cm2 which shows 80% reduction compared to previously reported values.

We consider storage channels that admit optional reading and rewriting of the content at a given cost. This is a general class of channels that models many nonvolatile memories. We present recent results on such rewritable channels with constraints on both the maximum and the average number of atomic rewrite iterations. We derive a general lower capacity bound for rewritable

Time- and temperature-dependent effects are critical for the operation of non-volatile memories based on ferroelectrics. In this paper, we assume a domain nucleation process of the polarization reversal and we discuss the polarization dynamics in the framework of a non-equilibrium statistical model. This approach yields analytical expressions which can be used to explain a wide range of time- and temperature-dependent effects in ferroelectrics. Domain wall velocity derived in this work is consistent with a domain wall creep behavior in ferroelectrics. In the limiting case of para-electric equilibrium, the model yields the well-known Curie law. We also present experimental P-E loops data obtained for soft ferroelectrics at various temperatures. The experimental coercive fields at various temperatures are well predicted by the coercive field formula derived in our theory.