Power Transistor

Electro-thermal simulation of power electronic semiconductors is now required in accurate optimisation of power electronic circuits and systems. This requires accurate, but not too complex, electro-thermal models of power semiconductors to be used in commercially available power electronic circuit simulators. Realization of one such electro-thermal model for power MOSFET in IsSpice is described in the paper. Model consists of electrical and thermal part with interactive exchange of variables. Electro-thermal model was tested on real circuit example.

The results presented in this paper are related to an experimental study that has the aim to evidence the formation of “latent gate oxide damages” in medium voltage power MOSFETs during the impact with energetic particles. The understanding of these “latent defectiveness” can be an helpful aid in the comprehension of the mechanisms of breach of the oxide layer of

Abstract— In many applications, it is desirable to integrate a power switch with an anti-parallel diode on the same chip. In this paper, monolithic integration of a SiC vertical JFET with a JBS diode is achieved and the device characterized at high voltage. The fabrication process ...

In the deep sub-micron domain wires consume more power than transistors. Power Gating for Wires is a form of bus segmentation that alleviates the power loss from on-chip interconnects, by switching off the supply voltage from inactive drivers, cycle by instruction-cycle. The success of Power Gating for Wires depends much on control: the gain from segmentation can conceivably be undone by control costs. Yet during design exploration, the data required for statistical analysis are not available. A theory of efficient control for Power Gating for Wires and a design framework, determining the balance of cost factors, at an early stage, are both needed. In this paper, we formulate a theory of Useful State Analysis to obtain minimal-redundancy encoding of control information. We establish two figures of merit, based on network topology: Intrinsic Sectioning Gain and Useful Encoding Efficiency. They quantify the power loss reduction achievable, and the success of Useful State Analysis in keeping control costs low. We propose a design pattern for the operation of a control plane, wherein the costs of control can be identified. From use cases, we find that architectures can have an Intrinsic Sectioning Gain of 50% and more. Useful Encoding Efficiency is found to be in a range of 44-80% for some common multipath architectures. Although ultimately, the limits of feasibility to control Power Gating for Wires must be decided by means of statistical analysis, we find Useful State Analysis is applicable to networks with tens of terminals, and that our method of control scales well with increasing network size and complexity.

- Photovoltaic ( PV ) generators exhibit non-linear insolation-dependent IV characteristics with poor voltage regulation. Because of their high cost, the user is interested in operating the generator close to its maxi-mum power. However, maximum-power point varies with ...

This work presents a theoretical analysis, validated by numerical simulations, of the vertical LOCOS DMOS structure. New analytical models of the specific on-state resistance and breakdown voltage are developed, which improve upon previous models in that an explicit dependence on device geometry and impurity concentration is worked out. The model accounts for the space charge due to the lateral and

In this brief, we propose a new dual-material-gate-trench power MOSFET that exhibits a significant improvement in its transconductance and breakdown voltage without any degradation in on-resistance. In the proposed structure, we have split the gate of a conventional trench MOSFET structure into two parts for work-function engineering. The two gates share the control of the inversion charge in the channel.

In this brief, we propose a new trench power MOSFET with strained-Si channel that provides lower on-resistance than the conventional trench MOSFET. Using a 20% Ge mole fraction in the Si 1-Ge x body with a compositionally graded Si 1-x Ge x buffer in the drift region enables us to create strain in the channel along with graded strain in the accumulation region.