RISC Processors

This paper presents the study of a simulated execution in several processors of the RISC architecture, its bechmark results, as well as fault statistics. MIPS, ARM, SPARC and PowerPC are widely used in embedded systems industry. Such a study evaluates the use of architectures and helps designers to define the architecture model in the construction of future hardware devices.

This paper presents the study of a simulated running on RISC processors , its bechmark results and conditional branches caused by these executions. MIPS and PowerPC are widely used in embedded systems industry. Such a study evaluates the use of architectures and helps designers to define the architecture model in the construction of future hardware devices.

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. The paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach

Instructions pipelining is one of the most outstanding techniques used in improving processor speed; nonetheless, these pipelined stages are constantly facing stalls that caused by nested conditional branches. During the execution of nested conditional branches, the behavior of the running branch depends on the history information of the previous ones; therefore, these branches have the greatest effect in reducing the prediction accuracy of a branch predictor among conditional branches. The purpose of this research is to reduce the stall cycles caused by correlated branches misprediction by introducing a hardware model of a branch predictor that combines both local and global prediction techniques. This predictor integrates the prediction characteristics of the alloyed predictor with those of the correlated predictor. the predictor design which implemented in VHDL (Very high-speed IC hardware description language) was inserted in previously designed MIPS (microprocessor without interlocked pipelined stages) processor and its prediction accuracy was confirmed by executing a program using the selection sort algorithm to sort 100 input numbers of different combinations ascendingly. Keywords: Alloyed predictor Correlated predictor Dynamic branch prediction FPGA MIPS Nested branches RISC processor VHDL This is an open access article under the CC BY-SA license.

We propose to look at the evolution of ideas related to parallel systems, algorithms, and applications during the past three decades and then glimpse at the future. The journey starts with massively parallel systems of the early nineties, transitions gently to computing for the masses on the clouds of the first decade of the new millennium, and continues with what we could expect from quantum computers and quantum parallelism in the next few decades. In the late 1980s several technology companies were tasked to build massively parallel systems for classified and unclassified work. Supercomputers built with high-performance processors and low-latency interconnection networks provided the computing cycles for a relatively small population of sophisticated users from National Laboratories and universities. For example, the Touchstone Delta and then the Paragon had a hypercube interconnection network connecting together hundreds or thousands i860s, RISC processors launched with great fanfare by Intel, but mostly forgotten today. Virtually all un-classified applications running on such systems required the development of parallel libraries and parallel algorithms for different areas of scientific computing. Well discuss in some depth an application in the area of structural biology we developed for the Touchstone Delta, the 3D structure determination of viruses with unknown symmetry at high resolution. The tide turned, and in the second half of the first decade of the new millennium utility computing captured the attention of the masses. Large farms of servers built with off-the-shelf components, the so-called clouds, appeared in different time zones on earth, rather than the sky, to support enterprize computing. Anybody with a credit card and a problem involving big data now had access to vast amounts of computing cycles and storage space. The number of Cloud Service Providers (CSPs), the spectrum of services offered by the CSPs, and the number of cloud users have increased dramatically during the last few years. For example, in 2007 the EC2 (Elastic Cloud Computing) was the first service provided by AWS (Amazon Web Services), five years later, in 2012, AWS was used by businesses in 200 countries. Amazons S3 (Simple Storage Service) has surpassed two trillion objects and routinely runs more than 1.1 million peak requests per second. Well-known methods to partition the data and process the data concurrently were rediscovered and given new names, the Elastic MapReduce service has launched 5.5 million clusters since the start of the service in May 2010. In our presentation well concentrate on the IaaS (Infrastructure as a Service) cloud delivery model, discuss several classes of applications running successfully on a cloud, and present the results of some cloud benchmarks. While the computer science and computer engineering communities were busy developing operating systems, file systems, compilers, and algorithms for parallel systems a physicist, albeit a very famous one, Richard Feynman, showed in 1982 that computers obeying the laws of classical physics will never be able to carry out some difficult tasks, for example, to exactly simulate a quantum system. He predicted that a system where information is encoded as properties of quantum particles and processed using reversible state transformations will be capable of delivering extraordinary computing power. A number of alternatives for building a quantum computer including quantum dots based on spin or charge, trapped ions in a cavity, liquid NMR (Nuclear Magnetic Resonance), quantum Hall effect, and other physical processes are now investigated in many labs around the world. The race to build a quantum computer is on. To understand why, we overview the physical phenomena exploited by quantum parallelism and then discuss Shors factoring algorithm which achieves an exponential speed-up compared with a classical one. In 2009 it took almost two years and hundreds of computers to factor a 768 bit number, it is estimated that it would take 1,000 times longer to factor a 1,024 bit number. A quantum computer would most likely be able to factor a 2,048 bit number in days. But, so far only quantum computers with few qubits were built thus, information encrypted with a few hundred bit keys is safe!!

This paper presents the integration issues of a proposed run-time configurable Memory Management Unit (MMU) to the COFFEE processor developed by our group at Tampere University of Technology. The MMU consists of three Translation Lookaside Buffers (TLBs) in two levels of hierarchy. The MMU and its respective integration to the processor is prototyped on a Field Programmable Gate Array (FPGA) device. Furthermore, analytical results of scaling the second-level Unified TLB (UTLB) to three configurations (with 16, 32, and 64 entries) with respect to the effect on overall hit rate as well as the energy consumption are shown. The critical path analysis of the logical design running on the target FPGA is presented together with a description of optimization techniques to improve static timing performance which leads to gain 22.75% speed-up. We could reach to our target operating frequency of 200 MHz for the 64-entry UTLB and, thus, it is our preferred option. The 32-entry UTLB configuration provides a decent trade-off for resource-constrained or speed-critical hardware designs while the 16-entry configuration poses unsatisfactory performance. Next, integration challenges and how to resolve each of them (such as employing a wrapper around the MMU, modifying the hardware description of the COFFEE core, etc.) are investigated in detail. This paper not only provides invaluable information with regard to the implementation and integration phases of the MMU to a RISC processor, it opens a new horizon to our processor to provide virtual memory for its running operating system without degrading the operating frequency. This work also tends toward being a general reference for future integration to the COFFEE core as well as other similar processor architectures.