The aim of this thesis is to research the di erences between the CSS preprocessor languages, namely Less and Sass, and find applicable transformation methods to implement a converter between their dynamic stylesheet formats. A general... more
The aim of this thesis is to research the di erences between the CSS preprocessor languages, namely Less and Sass, and find applicable transformation methods to implement a converter between their dynamic stylesheet formats. A general introduction to the concept of CSS preprocessors is provided first, which is followed by a thorough description of the Less and Sass language features. In addition to this, all the discovered differences are stated and illustrative examples of the invented conversion methods are provided in this work. This is followed by the description of the design and implementation of the proposed converter. As a part of the contribution of this thesis, a CSS comparison tool based on abstract syntax tree transformation has also been developed. Its design is described along the testing procedure used to verify the invented conversion methods. The last part of the work summarizes the achieved results and the future directions of the converter.
Miniaturization of transistors leads to increased chip density which allows integration of several applications in a small area. Increased performance, decreased propagation delay and improved device characteristics has increased demand... more
Miniaturization of transistors leads to increased chip density which allows integration of several applications in a small area. Increased performance, decreased propagation delay and improved device characteristics has increased demand of nanoscale CMOS fabrication in the deep submicron regime to support increased popularity of battery operated portable devices. Reduction in feature size of transistors results into increase in leakage current of sub threshold region. Thus leakage current becomes the primary means of dissipation of power for nanometer regime. In this paper, we have analyzed several leakage reduction techniques on CMOS Buf er circuit. CMOS Buf er circuit has several essential applications such as provision of interconnection between dif erent logic blocks, signal restoration while communicating over long wires, driving large capacitive loads or loads with low resistance to name a few. Buf ers are necessarily used to provide the output measurements of a chip. Hence, this forms an essential part of any logic circuit on a chip. We have found Sleepy CMOS-Sleepy Stack (SCSS) Technique to provide the best results with regard to reduction of delay in propagation, dissipation of static power and average power in comparison with Technique of Sleepy Stack (SST), Technique of Sleep Transistor (STT), Technique of Conventional CMOS (CCT), Technique of Forced Stack (FST), Technique of Dual Threshold Stack Transistor (DTST) and Technique of Sleepy Keeper (SKT). The simulations included in this paper were conducted in 45 nm technology using Virtuoso Tool of Cadence.
Building Information Modeling (BIM) may have obvious implications in the process of architectural design and construction at the present stage of technological development. However, BIM has rarely been really assessed and its benefits are... more
Building Information Modeling (BIM) may have obvious implications in the process of architectural design and construction at the present stage of technological development. However, BIM has rarely been really assessed and its benefits are often described in generic terms. In this paper we describe an experiment in which some benefits are identified from a comparison between two design processes of
