Surface Mount Technology

1. ABSTRACT The JPL-led CSP Consortium of enterprises representing government agencies and private companies has joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. Since last year, more than 150 test vehicles, single- and double-sided, have been assembled and are presently being subjected to various environmental tests.

In this article are presented results from the investigations of some peculiarities in the process of soldering on small topological forms in PCBs. The investigation is dedicated to the surface mount technology and deals with lead contained and lead free solder alloy pastes. Attention is paid on the implementation of contact pads with lead free surface finish. For this purpose are used galvanic deposited coatings and different solders. The results are obtained when using temperature profiles of typical production process at regimes, recommended by the solder paste vendors. In the experiments are implemented specially developed test lay outs and samples, manufactured from PCB material. Predominantly are investigated the processes of solder wetting in atmospheric surrounding.

This paper focuses on an integrated optimization problem that is designed to improve productivity in printed circuit board (PCB) manufacturing. We examine the problems of allocating the components to feeders and sequencing the placement of these components on the PCBs, populated by a rotary head machine with surface mount technology. While previous research focuses on sequencing the placement and only considers this subproblem as part of an interrelated set of problems, we provide an integrated approach which tackles all subproblems simultaneously as a single problem. Given an e-approximation algorithm for the vehicle routing problem we present a solution with an e-error gap for the

With the introduction of environmental legislation such as the Restriction of Hazardous Substances (RoHS), lead (Pb)-free materials have made their way into the electronics manufacturing industry. One issue that has emerged is that Pb-free solder alloys can initiate and grow tin whiskers under specific conditions. These whiskers are thin, highly conductive filaments which have the potential to grow and can cause field failures in many applications. Most concerning with respect to tin whiskering are high reliability applications such as aerospace, automotive, and medical. Bismuth (Bi) is being considered for inclusion in solder alloys to replace the current industry standard (SAC 305) and provide improved thermomechanical and vibration reliability. In this paper, we discuss whisker formation of several Bi-bearing alloys after long-term (12,000 hours), ambient high humidity (25°C/85% RH) storage. Three alloys containing Bi, in addition to SAC 305 (Sn-3.0Ag-0.5Cu), were considered.  Th...

A robotic remanufacturing system at Rensselaer has been developed to replace fine pitch surface mounted components on a populated printed circuit board (PCB). The performance goal is to maximize the quality of the solder joint output to optimize the system's throughput. The purpose of this paper is to present the process parameters determined for obtaining a good solder joint with the rework cell. Developed here and to show an analysis of the solder joint quality obtained from the developed system. Maximizing the rate of correctly reworked components by the system is not chosen as a goal for measuring the system's performance. This is because rework is a low volume process and the cell being used, is an experimental prototype system

To improve performance and reduce size of printed-circuit board (PCB) in electronics industry, embedding discrete components within a board substrate has been an effective approach by reducing solder joints and their associated impedance mismatching, inductive reactance, etc. With its unique capabilities for non-contact precision material deposition, the Aerosol Jet® direct-write technology has been enabling additive manufacturing of fine-feature electronics conformally onto flexible substrates of complicated shapes. The CAD/CAM controlled relative motions between substrate and print head allows convenient adjustment of the pattern and pile height of deposited material at a given ink volumetric deposition rate. To date in the printed electronics industry, additively printing embedded polymer-thick-film (PTF) resistors has mostly been done with screen printing using carbon-based paste inks. Here we demonstrate results of Aerosol Jet® printed PTF resistors of resistance values ranging...

In semiconductor manufacturing, wire bonding of chips and surface mount technology process require precise robotic linear motion. Traditionally, X-Y sliding tables driven by permanent magnet rotary motors, ball-screw and belt are used. However, they have position accuracy problem due to ball-screw backlash. Since motors and high precision grade ball-screws are expensive, high manufacturing cost is another disadvantage. Low reliability results

In this paper we show how hybrid control and modeling techniques can be put to work for solving a problem of industrial relevance in Surface Mount Technology (SMT) manufacturing. In particular, by closing the loop over the stencil printing process, we obtain a robust system that can recover from faulty initial settings, adapt to environmental changes and unscheduled interrupts, and remove discrepancies associated with bidirectional printing machines. Moreover, a timed Petri net argument is invoked for bounding the control effort in such a way that the throughput of the system is unaffected by the introduction of the closed-loop controller. The soundness of the approach is verified on a real SMT manufacturing line.

Increasing product complexity, decreasing component size, and using double-sided boards have made surface mount technology (SMT) based electronics manufacturing (EM) components more difficult to assemble. This has resulted in the economic troubleshooting of EM defects being one of the main problems facing all manufacturers. Although the authors have made significant improvements in the EM process, it has been shown that the implemented changes in the automated lines have not yet produced a high enough percentage of reliable finished products. The objective of this current development is to make a contribution towards these EM processes by creating an Internet-based intelligent system of circuit board defect detection so that EM process flaws that necessitate rework operations can be identified prior to manufacturing runs. With the development of this system, the need to rework the defective components will be minimized for any assembly line and assembly line process parameters, which cause some reliability problems (such as solder balls, insufficient solder at joints, burnt joint connections, bridged leads, voids, skewed leads, and unformed joints) will be troubleshot directly, and the rework will be greatly reduced from the EM assembly line. This paper reports the current development and its structure.

Motivation: As passive components’ size gets smaller, quality rejects due to overhangs after the reflow appear more frequently. This situation is partly because the pass-fail criterion is set based on the offset concerning the component and pad dimensions. Therefore, understanding the self-alignment characteristics of electronic components becomes very critical for surface-mount assembly yield. This research investigates the dissimilarity of selfalignment in the length and width directions. Approach: To avoid the argument of sample to sample variations, data are collected from 81 printed circuit boards (PCB) and 182,250 assembled components. Within a PCB, 25 different solder paste printing offset locations and 81 component placement offset settings are implemented. Component-placement positions before and after the reflow are monitored. The results are compared to identify different component sizes’ self-alignment characteristics in the length and width directions. Key findings: The...

1. ABSTRACT The JPL-led CSP Consortium of enterprises representing government agencies and private companies has joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. Since last year, more than 150 test vehicles, single- and double-sided, have been assembled and are presently being subjected to various environmental tests.

As Cisco’s next-generation products continue to push the trends of higher signal speeds and increased functional density, the need for advanced PCB structures, such as Via-in-Pad Plated Over (VIPPO) and backdrill, and high-speed memory is becoming more mainstream across product platforms.  Furthermore, as these high-speed memory technologies are being driven by consumer applications, the form factor and interconnect pitches continue to shrink to meet the demands of the mobile device market.  The use of these advanced PCB structures, like VIPPO and VIPPO with backdrill, within the BGA footprints, particularly for the fine pitch patterns, have been found to result in BGA solder separation defects at the bulk solder to IMC interface upon a 2nd reflow, e.g. during top-side reflow for bottom-side components or during rework of an adjacent BGA.1  In some cases, this solder separation failure mode has also been identified with buried vias under the BGA pad or even without the presence of V...

The fundamental ability to drive automatically to independent locations and deposit controlled masses of electronics packaging adhesives makes dispensing an attractive solution in the electronics assembly. The existence of modern technology such as smartphones, wearable devices (watches, glasses, etc.), and tablets have led to tightly spaced, and high-density component packaging which further causes complex designs in the Printed Circuit Board (PCB) assembly. Advancements in dispensing technology because of these growing challenges in assembly has led to use of jetting systems in this new arena. The process of jetting, unlike traditional dispensing, has the ability to deposit controlled masses of packaging adhesives (also known as packaging fluids) at tightly spaced locations with high accuracy and high speed and at much higher deposition heights from the substrate. In this article, a voice-coil-driven jetting system is studied to assess the capability of jetting micrograms of electronics packaging fluids. The article presents experimental analyses to study jetting of micrograms of fluid droplets. Critical input factors are evaluated using a split-plot design of experiment (DOE) model to understand their significance in governing the responses. The responses studied in this work are the following: mass per droplet, dot diameter, and dispense quality. The applied DOE model will assist in developing prediction models to determine the optimal combination of factors in achieving desired responses.

This paper focuses on an integrated optimization problem that is designed to improve productivity in printed circuit board (PCB) manufacturing. We examine the problems of allocating the components to feeders and sequencing the placement of these components on the PCBs, populated by a rotary head machine with surface mount technology. While previous research focuses on sequencing the placement and only

A method is proposed to realize cavity resonator filters for cellular frequencies in surface-mount technology. The cavity resonators can be produced by molding techniques and subsequently soldered onto a circuit board, where a stripline structure in the circuit board makes the coupling between the resonators. The molded parts for all resonators of a given filter can be identical. Means are

Abstract: To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been required. In process development, experiences learned from flip chip attach and ball grid array (BGA) ...