Content Addressable Memory (CAM) is used as a hardware search engine. Ternary CAM (TCAM) has numerous applications compared to Binary CAM (BiCAM) but TCAM requires more power than Binary CAM. Therefore, many TCAM designers are focused on... more
Content Addressable Memory (CAM) is used as a hardware search engine. Ternary CAM (TCAM) has numerous applications compared to Binary CAM (BiCAM) but TCAM requires more power than Binary CAM. Therefore, many TCAM designers are focused on its power reduction. TCAM consumes more power because of its precharge phase and series connection of TCAM cells results more delay. Here, different TCAM architectures have been implemented for 64 bits. Each architecture has its own merits and demerits. The different TCAM architectures have been compared for different bits in terms of speed and power. Simulations are performed with the help of cadence 45-nm technology at 1V supply.
Ternary content addressable memory (TCAM) is a memory with some special characteristics. TCAM performs high speed parallel search operations and the operation done in single clock cycle. But TCAM having some limitations as compared with... more
Ternary content addressable memory (TCAM) is a memory with some special characteristics. TCAM performs high speed parallel search operations and the operation done in single clock cycle. But TCAM having some limitations as compared with SRAM, which are low storage density, circuit complexity and slow access time. So, further we can move to TCAM with hybrid partition, as Z-TCAM. This paper proposes TCAM functionality with SRAM. Here hybrid partition of stored data in memory blocks is more important. Hybrid partition is main reason of shrinking the size of the memory and latency time. The language used for verifying proposed implementation is Verilog /VHDL.
What is claimed is: 1. A method comprising: storing, at a network element, a plurality of merged forwarding entries, a merged forwarding entry formed by merging information from at least one load balancing entry and at least one access... more
What is claimed is: 1. A method comprising: storing, at a network element, a plurality of merged forwarding entries, a merged forwarding entry formed by merging information from at least one load balancing entry and at least one access control list (ACL) entry; receiving, at the network element, a packet of data after the plurality of merged forwarding entries are stored; parsing at least one field from the packet of data; identifying a merged forwarding entry from the plurality of merged forwarding entries based on the at least one field; and forwarding the packet of data through a port of the network element in accordance with the identified merged forwarding entry. 2. The method of claim 1, wherein the information from the at least one ACL entry specifies at least one address and an indication to permit traffic associated with the at least one address. 3. The method of claim 1, wherein the information from the at least one ACL entry specifies at least one address and an indication to deny traffic associated with the at least one address. 4. The method of claim 1, wherein the information from the at least one load balancing entry comprises an egress port of the network element and at least one address. ABSTRACT In one embodiment a packet of data is received at a network element. At least one field is parsed from the packet of data. A forwarding entry is identified from a plurality of forwarding entries based on the at least one field. The forwarding entry of the plurality of forwarding entries is formed by merging information from at least one load balancing entry and at least one access control list (ACL) entry. The data packet is forwarded through a port of the network element in accordance with the identified forwarding entry. This disclosure relates in general to the field of communications and, more particularly, to utilizing userspecified access control lists in conjunction with redirection and loadbalancing on a port. BACKGROUND
Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an... more
Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multi- cycle compare operations, half/quarter words and walking patterns. Keywords-CAM; BCAM; TCAM; BIST architecture; fault; March test algorithm
Embodiments include receiving configuration information including a match criterion for packets received at a network device in a network and a pool of layer 3 addresses associated with a set of servers in the network, resolving layer 2... more
Embodiments include receiving configuration information including a match criterion for packets received at a network device in a network and a pool of layer 3 addresses associated with a set of servers in the network, resolving layer 2 destination addresses based on the layer 3 addresses of the servers, and programming a hardware layer of the network device based, at least in part, on the match criterion, the pool of layer 3 addresses, and the layer 2 destination addresses. Specific embodiments include configuring a policy to indicate that packets from an external source are to be forwarded to a server of the set of servers. Further embodiments include receiving a packet at the network device, and matching the packet to the pool of layer 3 addresses and the resolved layer 2 addresses based, at least in part, on the match criterion programmed in the hardware layer.
