Task Scheduling in Heterogeneous Computing Systems

Makespan minimization in tasks scheduling of infrastructure as a service (IaaS) cloud is an NP-hard problem. A number of techniques had been used in the past to optimize the makespan time of scheduled tasks in IaaS cloud, which is propotional to the execution cost billed to customers. In this paper, we proposed a League Championship Algorithm (LCA) based makespan time minimization scheduling technique in IaaS cloud. The LCA is a sports-inspired population based algorithmic framework for global optimization over a continuous search space. Three other existing algorithms that is, First Come First Served (FCFS), Last Job First (LJF) and Best Effort First (BEF) were used to evaluate the performance of the proposed algorithm. All algorithms under consideration assumed to be non-preemptive. The results obtained shows that, the LCA scheduling technique perform moderately better than the other algorithms in minimizing the makespan time of scheduled tasks in IaaS cloud.

This research work is a pair review into the conceptual frame work and innovation into Pen-style Personal Network Gadget Package (P-ISM) as inevitable tool to easy, fast and convenient access to the internet.
Computing activities have increased the degree of people using personal computers (PCs), complicated packages and all form of social media applications (Apps.) have emerged within this short period. Meeting
these trends (day to day activities) in more convenient form has led to the modern sophisticated garget such as Pen-Style Network Gadget Package (P-ISM) prototype. The growth in internet affects our lives in
much better way than we know and its sustainability made 5 pen technology innovations a salt after.

In today’s scenario, wireless network is mainly used
in those areas where infrastructure based networks are
unavailable. The mobile ad-hoc network (MANET) is the mobile
network where infrastructure is not required and nodes can be
connected in random manner[1]. In MANET, sensor networks
are incarnated in which mobile nodes have sensing capability. Ad
hoc On demand Distance Vector (AODV), Dynamic Destination
Sequenced Distance Vector (DSDV), Dynamic Source Routing
(DSR) are well know communication protocol of wireless sensor
network. These conventional protocols use shortest path or
minimum hop count for path selection to transfer a packet from
source to destination but those sensor networks which requires
high quality of service(QoS),works over several criteria’s and
possibilities which could affect the quality of path selection
service. The QoS is affected by a certain number of parameters
like delay, bandwidth, jitter, throughput, latency and packet loss
etc. In this paper we analysis currently exist delay aware routing
protocols focusing at route selection mechanism & their solution.
This analytical learning could be very fruitful for future
enhancement in AODV.

En este trabajo se presenta un modelo de programación lineal entera mixta (MILP) para el problema de asignación de tareas independientes en ambientes de cómputo heterogéneo (HCSP) con energía. Para el control de la energía se usa la técnica de escalamiento dinámico de voltaje y frecuencia (DVFS). El modelo lineal sigue un orden jerárquico de dos fases en cual primero se minimiza el tiempo en que termina la última tarea (makespan) y después el consumo total de energía.

This paper proposes a new scheduling technique for digital signal processing (DSP) applications represented by data flow graphs (DFGs). Hardware implementation in the form of a specialized embedded system, is proposed. The scheduling technique achieves the optimal schedule of a given DFG at design time. The optimality criterion targeted in the proposed algorithm is the maximum throughput than can be achieved by the available hardware resources. Each task is presented in a form of an instruction to be executed on the available hardware. The architecture is composed of one or multiple homogeneous pipelined processing elements, designed to achieve the maximum possible sampling rate for several DSP applications. In this paper, we present a processor implementation of the proposed architecture. It comprises one processing element where all tasks are processed sequentially. The hardware components are built on an FPGA chip using Verilog HDL. The architecture requires a very small area size, which is represented by the number of slice registers and the number of slice lookup tables (LUTs). The proposed scheduling technique is shown to outperform the retiming technique, which is proposed in the literature, by 19.3%.

High Speed computing meets ever increasing real-time computational demands through the leveraging of
flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications.

The current state and foreseeable future of high performance scientific computing (HPC) can be described in three words: heterogeneous, parallel and distributed. These three simple words have a great impact on the architecture and design of HPC platforms and the creation and execution of efficient algorithms and programs designed to run on them. As a result of the inherent heterogeneity, parallelism and distribution which promises to continue to pervade scientific computing in the coming years, the issue of data distribution and therefore data partitioning is unavoidable. This data distribution and partitioning is due to the inherent parallelism of almost all scientific computing platforms. Cluster computing has become all but ubiquitous with the development of clusters of clusters and grids becoming increasingly popular. Even at a lower level, high performance symmetric multiprocessor (SMP) machines, General Purpose Graphical Processing Unit (GPGPU) computing, and multiprocessor pa...

This paper proposes a new scheduling technique for digital signal processing (DSP) applications represented by data flow graphs (DFGs). Hardware implementation in the form of a specialized embedded system, is proposed. The scheduling technique achieves the optimal schedule of a given DFG at design time. The optimality criterion targeted in the proposed algorithm is the maximum throughput than can be achieved by the available hardware resources. Each task is presented in a form of an instruction to be executed on the available hardware. The architecture is composed of one or multiple homogeneous pipelined processing elements, designed to achieve the maximum possible sampling rate for several DSP applications. In this paper, we present a processor implementation of the proposed architecture. It comprises one processing element where all tasks are processed sequentially. The hardware components are built on an FPGA chip using Verilog HDL. The architecture requires a very small area siz...

High Speed computing meets ever increasing real-time computational demands through the leveraging of
flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications