Search Results (2,008)

A large number of fully normalized associated Legendre function (fnALF) calculations are required to compute Earth’s gravity field elements using ultra high-order gravity field coefficient models. In the surveying and mapping industry, researchers typically rely on CPU-based systems for these calculations, which leads to limitations in execution speed and power efficiency. Although modern CPUs improve instruction execution efficiency through instruction-level parallelism, the constraints of a shared memory architecture impose further limitations on the execution speed and power efficiency. This results in exponential increases in computation time as demand rises alongside high power consumption. In this article, we present a new computational implementation of an fnALF based on the ZYNQ platform. We design a task-parallel “pipeline” architecture which converts the original serial logic into a more efficient hardware implementation, and we utilize a redundant calculation layer to handle repetitive coefficient computations separately. The experimental results demonstrate that our system achieved accurate and rapid calculations. Under the only one geocentric residual latitude condition, we measured the computation times for spherical harmonic coefficient degrees of 360, 720, and 1080 to be 0.155922 s, 0.520950 s, and 1.401609 s, respectively. In the case of the multiple geocentric residual latitudes condition, our design generally yielded efficiency gains of over three times those of MATLAB R2020b implementation. Additionally, our calculated results were used to determine the geoid height in the field with an error of less than $\pm 0.1\mathrm{m}$, confirming the reliability of our computations. Full article

This paper presents a programmable digital filtering unit dedicated to operating with signals from infrared (IR) detection modules. The designed device is quite useful for increasing the signal-to-noise ratio due to the reduction in noise and interference from detector–amplifier circuits or external radiation sources. Moreover, the developed device is flexible due to the possibility of programming the desired filter types and their responses. In the circuit, an advanced field-programmable gate array FPGA chip was used to ensure an adequate number of resources that are necessary to implement an effective filtration process. The proposed circuity was assisted by a 32-bit microcontroller to perform controlling functions and could operate at frequency sampling of up to 40 MSa/s with 16-bit resolution. In addition, in our application, the sampling frequency decimation enabled obtaining relatively narrow passband characteristics also in the low frequency range. The filtered signal was available in real time at the digital-to-analog converter output. In the paper, we showed results of simulations and real measurements of filters implementation in the FPGA device. Moreover, we also presented a practical application of the proposed circuit in cooperation with an InAsSb mid-IR detector module, where its self-noise was effectively reduced. The presented device can be regarded as an attractive alternative to the lock-in technique, artificial intelligence algorithms, or wavelet transform in applications where their use is impossible or problematic. Comparing the presented device with the previous proposal, a higher signal-to-noise ratio improvement and wider bandwidth of operation were obtained. Full article

Approximate Computing (AxC) has emerged as a promising paradigm to enhance performance and energy efficiency by allowing a controlled trade-off between accuracy and resource consumption. It is extensively adopted across various abstraction levels, from software to architecture and circuit levels, employing diverse methodologies. The primary objective of AxC is to reduce energy consumption for executing error-resilient applications, accepting controlled and inherently acceptable output quality degradation. However, harnessing AxC poses several challenges, including identifying segments within a design amenable to approximation and selecting suitable AxC techniques to fulfill accuracy and performance criteria. This survey provides a comprehensive review of recent methodologies proposed for performing Design Space Exploration (DSE) to find the most suitable AxC techniques, focusing on both hardware and software implementations. DSE is a crucial design process where system designs are modeled, evaluated, and optimized for various extra-functional system behaviors such as performance, power consumption, energy efficiency, and accuracy. A systematic literature review was conducted to identify papers that ascribe their DSE algorithms, excluding those relying on exhaustive search methods. This survey aims to detail the state-of-the-art DSE methodologies that efficiently select AxC techniques, offering insights into their applicability across different hardware platforms and use-case domains. For this purpose, papers were categorized based on the type of search algorithm used, with Machine Learning (ML) and Evolutionary Algorithms (EAs) being the predominant approaches. Further categorization is based on the target hardware, including Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), general-purpose Central Processing Units (CPUs), and Graphics Processing Units (GPUs). A notable observation was that most studies targeted image processing applications due to their tolerance for accuracy loss. By providing an overview of techniques and methods outlined in existing literature pertaining to the DSE of AxC designs, this survey elucidates the current trends and challenges in optimizing approximate designs. Full article

Binarized convolutional neural networks (bCNNs) are favored for the design of low-storage, low-power cardiac arrhythmia classifiers owing to their high weight compression rate. However, multi-class classification of ECG signals based on bCNNs is challenging due to the accuracy loss introduced by the binarization operation. In this paper, an effective multi-classifier system is proposed for electrocardiogram (ECG) signals using a binarized depthwise separable convolutional neural network (bDSCNN) with the merged convolution–pooling (MCP) method. The binarized depthwise separable convolution layer is adopted to reduce the increased number of parameters in multi-classification systems. Instead of operating convolution and pooling sequentially as in a traditional convolutional neural network (CNN), the MCP method merges pooling together with convolution layers to reduce the number of computations. To further reduce hardware resources, this work employs blockwise incremental calculation to eliminate redundant storage with computations. In addition, the R peak interval data are integrated with P-QRS-T features to improve the classification accuracy. The proposed bDSCNN model is evaluated on an Intel DE1-SoC field-programmable gate array (FPGA), and the experimental results demonstrate that the proposed system achieves a five-class classification accuracy of 96.61% and a macro-F1 score of 89.08%, along with a dynamic power dissipation of 20 μW for five-category ECG signal classification. The hardware resource usage of BRAM and LUTs plus REGs is reduced by at least 2.94 and 1.74 times, respectively, compared with existing ECG classifiers using bCNN methods. Full article

A cyclic redundancy check (CRC) is a widely used technique in data communication for detecting data transmission errors. However, existing FPGA-based parallel CRC hardware implementation schemes often face problems of excessive resource utilization and timing convergence difficulties in high-bandwidth networks. In addition, these problems are further exacerbated by the variable length of the end of the checksum data frame during data transmission. To address these challenges, this paper proposes a parallel CRC computation method based on precomputed seed values for bit-width normalization (named PSV-WN-CRC). The algorithm selects the corresponding primitive seed value according to the length of the data frame tail and converts the CRC computation with arbitrary bit-width to the CRC computation with fixed bit-width, thus adapting to the case of the indefinite length of the data frame tail. Based on this algorithm, this paper designs an efficient parallel CRC circuit on FPGA to reduce the consumption of resources. The experimental results show that the CRC algorithm and circuit proposed in this paper implemented on Virtex UltraScale+ FPGAs with 1024-bit wide CRC consumes only 5981 LUTs and achieves a maximum throughput of 392.2 Gbps. The method effectively reduces the resource consumption and improves the maximum throughput as compared to three advanced works. Full article

In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore, the input stream is truncated with an erratum mending unit to roughly construct the partial products. For an aggregation of PPs, an approximate Wallace tree is taken into consideration to further minimize hardware expenses. Consequently, the suggested design’s latency, utilized area, and power usage are largely reduced. The Xilinx Vertex device is expedited, given the synthesis of the suggested multichannel realization with 16 taps, which is simulated using the Verilog formulary. It is observed that the filter structure with one channel produced the desired results, and the system’s frequency can support up to 429 MHz with a reduced area. Utilizing TSMC 180 nm CMOS technology and the Cadence RC compiler, cell-level performance is also achieved. Full article

During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Despite achieving significant results, improvement in these factors is still a challenging task. Recently, an emerging computational area has been seen as a potential solution to improving the performance of conventional binary circuits. In particular, this area uses a method based on spiking neural P systems (SN P) to create arithmetic circuits, such as adders, subtractors, multipliers, and divisors, since these components are vital in many IoT applications. To date, several efforts have been dedicated to decreasing the number of neurons and synapses to create compact circuits. However, processing speed is a persistent issue. In this work, we propose four compact arithmetic circuits with high processing speeds. To evaluate their performance, we designed a neuromorphic processor that is capable of performing four operations using dynamic connectivity. As a consequence, the proposed neuromorphic processor achieves higher processing speeds by maintaining low area consumption in comparison with the existing approaches. Full article

The fusion energy research field presents many intricate challenges that require resolution. Many diagnostic systems employed in experiments are approaching the limits of current technology. Implementing efficient measurements requires using an appropriate set of tools to facilitate the optimal utilization of hardware. Fusion energy measurements must provide low latency processing with the capacity for future improvements and the ability to handle complex data flows efficiently. The presented work addresses these requirements and describes the implementation of a high-performance, low-latency software platform with convenient development for soft X-ray (SXR) plasma impurities emission tracing—the Asynchronous Complex Computation Platform (AC2P). This article presents the architectural design, implementation details, and performance and latency measurements based on the raw data acquired from the WEST tokamak and laboratory tests. AC2P provides the tools to develop low-latency, multi-core, multi-device complex data flow graph scale-up solutions for measuring impurities in hot plasmas. The system has been designed to operate online during experiments, calculate the energy distribution, position and occurrence time of SXR photons, monitor the data stream’s quality and archive any abnormalities for subsequent offline verification and algorithm improvement. This article presents AC2P, which operates as part of the SXR measurement system on the WEST tokamak. Full article

Nowadays, M-Quadrature Amplitude Modulation (M-QAM) techniques are widely used to modulate information by bit packets due to their ability to increase transfer rates. These techniques require more power when increasing the modulation index M to avoid interference between symbols. This article proposes a technique that does not suffer from interference between symbols, but instead uses memory elements to store the modulation symbols. In addition, the aim of this paper is to implement a four-dimensional reconfigurable chaotic oscillator that generates 16-Chaotic Phase Shift Keying (16-CPSK) modulation–demodulation carriers. An encryption and modulation transmitter module, a reception module, and a master–slave Hamiltonian synchronization module make up the system. A 16-CPSK modulation scheme implemented in Field Programmable Gate Array (FPGA) and applied to a red-green-blue (RGB) and grayscale image encryption system are the main contributions of this work. Matlab and Vivado were used to verify the modulation–demodulation scheme and synchronization. This proposal achieved excellent correlation coefficients according to various investigations, the lowest being $-15.9\times {10}^{-6}$ and $0.13\times {10}^{-3}$ for RGB and grayscale format images, respectively. The FPGA implementation of the 16-CPSK modulation–demodulation system was carried out using a manufacturer’s card, Xilinx’s Artix-7 AC701 (XC7A200TFBG676-2). Full article

This research presents a sleep posture monitoring system designed to assist the elderly and patient attendees. Monitoring sleep posture in real time is challenging, and this approach introduces hardware-based edge computation methods. Initially, we detected the postures using minimally optimized sensing modules and fusion techniques. This was achieved based on subject (human) data at standard and adaptive levels using posture-learning processing elements (PEs). Intermittent posture evaluation was performed with respect to static and adaptive PEs. The final stage was accomplished using the learned subject posture data versus the real-time posture data using posture classification. An FPGA-based Hierarchical Binary Classifier (HBC) algorithm was developed to learn and evaluate sleep posture in real time. The IoT and display devices were used to communicate the monitored posture to attendant/support services. Posture learning and analysis were developed using customized, reconfigurable VLSI architectures for sensor fusion, control, and communication modules in static and adaptive scenarios. The proposed algorithms were coded in Verilog HDL, simulated, and synthesized using VIVADO 2017.3. A Zed Board-based field-programmable gate array (FPGA) Xilinx board was used for experimental validation. Full article

This study developed a realization of sensorless control for a permanent magnet synchronous motor (PMSM) using a field-programmable gate array (FPGA). Both position and speed were estimated using a high-frequency (HF) injection scheme. Accurate estimation is essential to ensure the proper functioning of sensorless motor control. To improve the estimation accuracy of the rotor position and reduce the motor speed ripple found in conventional methods, a new extraction strategy for estimating the rotor position and motor speed is proposed. First, signal modulation compensation was applied to expand the information of the error function in order to provide more accurate data to the tracking loop system for rotor position extraction. Second, to minimize the motor speed ripple caused by the HF injection, motor speed estimation was performed after obtaining the rotor position information using a differential equation with a low-pass filter (LPF) to avoid the direct effect of the injected signal. Verified experimentally, the results showed that the rotor position error did not exceed 10 el.deg, so these methods effectively reduce the rotor position estimation error by about 30%, along with the motor speed ripple. Therefore, better performance in sensorless PMSM control can be achieved in motor control applications. Full article

Remote laboratories are essential in addressing access and quality challenges in technical education. They enable students from various locations to engage with real equipment, overcome geographic and economic constraints, and provide solutions during crises, such as pandemics, when in-person learning is limited. As a key element of Education 4.0, remote labs promote technical skill development, enhance engineering education, and support diverse learning approaches. This study presents a remote laboratory based on Field Programmable Gate Arrays (FPGAs), developed using a waterfall methodology integrating IoT and Cloud Computing technologies to facilitate close interaction between hardware and software. The lab focuses on controlling DC, servo, and stepper motors, allowing students to apply theoretical concepts such as digital signals, pulse-width modulation (PWM), and data representation in bits in a practical setting. The testing phase involved 50 robotics and mechatronics engineering students who participated in hands-on sessions for one month, followed by a structured survey evaluating their experience, interaction, and the educational relevance of the platform. The survey shows high student satisfaction, highlighting the platform’s strengths and identifying areas for improvement. The results also underscore the system’s potential to significantly enhance the educational experience in remote environments, aligning with the United Nations Sustainable Development Goals (SDGs). Full article

We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (SRLMS), and the second algorithm “Split-Row Threshold Layered Min-Sum” (SRTLMS). A threshold message passes from one partition to another in SRTLMS, minimizing the gap from the MS and achieving a binary error rate of 3 × 10⁻⁵ with Imax = 4 as the maximum number of iterations, resulting in a decrease of 0.25 dB. The simulation’s findings indicate that the SRTLMS is the most efficient variant decoding algorithm for LDPC codes, thanks to its compromise between performance and complexity. This paper presents the two invented algorithms and a comprehensive study of the co-design and implementation of the SRTLMS algorithm. We executed the implementation on a Xilinx Kintex-7 XC7K160 FPGA, achieving a maximum operating frequency of 101 MHz and a throughput of 606 Mbps. Full article

The exponential growth and widespread adoption of Internet of Things (IoT) devices have introduced many vulnerabilities. Attackers frequently exploit these flaws, necessitating advanced technological approaches to protect against emerging cyber threats. This paper introduces a novel approach utilizing hardware honeypots as an additional defensive layer against hardware vulnerabilities, particularly hardware Trojans (HTs). HTs pose significant risks to the security of modern integrated circuits (ICs), potentially causing operational failures, denial of service, or data leakage through intentional modifications. The proposed system was implemented on a Raspberry Pi and tested on an emulated HT circuit using a Field-Programmable Gate Array (FPGA). This approach leverages hardware honeypots to detect and mitigate HTs in the IoT devices. The results demonstrate that the system effectively detects and mitigates HTs without imposing additional complexity on the IoT devices. The Trojan-agnostic solution offers full customization to meet specific security needs, providing a flexible and robust layer of security. These findings provide valuable insights into enhancing the security of IoT devices against hardware-based cyber threats, thereby contributing to the overall resilience of IoT networks. This innovative approach offers a promising solution to address the growing security challenges in IoT environments. Full article

This work presents a novel fully parallel decoder architecture designed for high-throughput decoding of Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes within the context of 5G New-Radio (NR) communication. The design uses the layered Min-Sum (MS) algorithm and focuses on increasing throughput to meet the strict needs of enhanced Mobile BroadBand (eMBB) applications. We incorporated a Sub-Optimal Low-Latency (SOLL) technique to enhance the critical check node processing stage inherent to the MS algorithm. This technique efficiently computes the two minimum values, rendering the architecture well-suited for specific Ultra-Reliable Low-Latency Communication (URLLC) scenarios. We design the decoder to be reconfigurable, enabling efficient operation across all expansion factors. We rigorously validate the decoder’s effectiveness through meticulous bit-error-rate (BER) performance evaluations using Hardware Description Language (HDL) co-simulation. This co-simulation utilizes a well-established suite of tools encompassing MATLAB/Simulink for system modeling and Vivado, a prominent FPGA design suite, for hardware representation. With 380,737 Look-Up Tables (LUTs) and 32,898 registers, the decoder’s implementation on a Virtex-7 XC7VX980T FPGA platform by AMD/Xilinx shows good hardware utilization. The architecture attains a robust operating frequency of 304.5 MHz and a normalized throughput of 49.5 Gbps, marking a 36% enhancement compared to the state-of-the-art. This advancement propels decoding capabilities to meet the demands of high-speed data processing. Full article