Features

High-performance, Low-power AVR 8-bit Microcontroller Advanced RISC Architecture

131 Powerful Instructions Most Single-clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments 16K Bytes of In-System Self-programmable Flash program memory 512 Bytes EEPROM 1K Bytes Internal SRAM Write/Erase cycles: 10,000 Flash/100,000 EEPROM Data retention: 20 years at 85C/100 years at 25C(1) Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation Up to 64K Bytes Optional External Memory Space Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and Capture Modes Real Time Counter with Separate Oscillator Six PWM Channels Dual Programmable Serial USARTs Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby I/O and Packages 35 Programmable I/O Lines 40-pin PDIP, 44-lead TQFP, and 44-pad MLF Operating Voltages 1.8 - 5.5V for ATmega162V 2.7 - 5.5V for ATmega162 Speed Grades 0 - 8 MHz for ATmega162V (see Figure 113 on page 266) 0 - 16 MHz for ATmega162 (see Figure 114 on page 266)

8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATmega162 ATmega162V Summary

Pin Configurations

Figure 1. Pinout ATmega162

PDIP (OC0/T0) PB0 (OC2/T1) PB1 (RXD1/AIN0) PB2 (TXD1/AIN1) PB3 (SS/OC3B) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 (TXD0) PD1 (INT0/XCK1) PD2 (INT1/ICP3) PD3 (TOSC1/XCK0/OC3A) PD4 (OC1A/TOSC2) PD5 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PA0 (AD0/PCINT0) PA1 (AD1/PCINT1) PA2 (AD2/PCINT2) PA3 (AD3/PCINT3) PA4 (AD4/PCINT4) PA5 (AD5/PCINT5) PA6 (AD6/PCINT6) PA7 (AD7/PCINT7) PE0 (ICP1/INT2) PE1 (ALE) PE2 (OC1B) PC7 (A15/TDI/PCINT15) PC6 (A14/TDO/PCINT14) PC5 (A13/TMS/PCINT13) PC4 (A12/TCK/PCINT12) PC3 (A11/PCINT11) PC2 (A10/PCINT10) PC1 (A9/PCINT9) PC0 (A8/PCINT8)

TQFP/MLF
PB4 (SS/OC3B) PB3 (TXD1/AIN1) PB2 (RXD1/AIN0) PB1 (OC2/T1) PB0 (OC0/T0) GND VCC PA0 (AD0/PCINT0) PA1 (AD1/PCINT1) PA2 (AD2/PCINT2) PA3 (AD3/PCINT3)

(MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 VCC (TXD0) PD1 (INT0/XCK1) PD2 (INT1/ICP3) PD3 (TOSC1/XCK0/OC3A) PD4 (OC1A/TOSC2) PD5

44 42 40 38 36 34 43 41 39 37 35 33 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 13 15 17 19 21 12 14 16 18 20 22
(WR) PD6 (RD) PD7 XTAL2 XTAL1 GND VCC (A8/PCINT8) PC0 (A9/PCINT9) PC1 (A10/PCINT10) PC2 (A11/PCINT11) PC3 (TCK/A12/PCINT12) PC4

PA4 (AD4/PCINT4) PA5 (AD5/PCINT5) PA6 (AD6/PCINT6) PA7 (AD7/PCINT7) PE0 (ICP1/INT2) GND PE1 (ALE) PE2 (OC1B) PC7 (A15/TDI/PCINT15) PC6 (A14/TDO/PCINT14) PC5 (A13/TMS/PCINT13)

NOTE: MLF bottom pad should be soldered to ground.

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

ATmega162/V
2513JSAVR08/07

ATmega162/V
Overview
The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2. Block Diagram
PA0 - PA7 VCC PE0 - PE2 PC0 - PC7

Block Diagram

PORTA DRIVERS/BUFFERS

PORTE DRIVERS/ BUFFERS

PORTC DRIVERS/BUFFERS

GND

PORTA DIGITAL INTERFACE

PORTE DIGITAL INTERFACE

PORTC DIGITAL INTERFACE

PROGRAM COUNTER

STACK POINTER

INTERNAL OSCILLATOR XTAL1

PROGRAM FLASH

SRAM

WATCHDOG TIMER

OSCILLATOR

XTAL2 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X INSTRUCTION DECODER Y Z INTERRUPT UNIT MCU CTRL. & TIMING RESET

INTERNAL CALIBRATED OSCILLATOR

CONTROL LINES

ALU

TIMERS/ COUNTERS

OSCILLATOR

AVR CPU

STATUS REGISTER

EEPROM

PROGRAMMING LOGIC

SPI

USART0

+ -

COMP. INTERFACE

USART1

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

3
2513JSAVR08/07

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega162 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an external memory interface, 35 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, four flexible Timer/Counters with compare modes, internal and external interrupts, two serial programmable USARTs, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmels high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot Program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.

ATmega161 and ATmega162 Compatibility

The ATmega162 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure back-ward compatibility with the ATmega161, all I/O locations present in ATmega161 have the same locations in ATmega162. Some additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega161 users. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega161 compatibility mode can be selected by programming the fuse M161C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega161. Also, the Extended Interrupt Vec-tors are removed. The ATmega162 is 100% pin compatible with ATmega161, and can replace the ATmega161 on current Printed Circuit Boards. However, the location of Fuse bits and the electrical characteristics differs between the two devices. Programming the M161C will change the following functionality: The extended I/O map will be configured as internal RAM once the M161C Fuse is programmed.

ATmega161 Compatibility Mode

ATmega162/V
2513JSAVR08/07

ATmega162/V
The timed sequence for changing the Watchdog Time-out period is disabled. See Timed Sequences for Changing the Configuration of the Watchdog Timer on page 56 for details. The double buffering of the USART Receive Registers is disabled. See AVR USART vs. AVR UART Compatibility on page 168 for details. Pin change interrupts are not supported (Control Registers are located in Extended I/O). One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible.

Note that the shared UBRRHI Register in ATmega161 is split into two separate registers in ATmega162, UBRR0H and UBRR1H. The location of these registers will not be affected by the ATmega161 compatibility fuse.

Pin Descriptions
VCC GND Port A (PA7..PA0) Digital supply voltage Ground Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega162 as listed on page 72. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega162 as listed on page 72. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be activated even if a Reset occurs. Port C also serves the functions of the JTAG interface and other special features of the ATmega162 as listed on page 75.

5
2513JSAVR08/07

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega162 as listed on page 78.

Port E(PE2..PE0)

Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega162 as listed on page 81.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 18 on page 48. Shorter pulses are not guaranteed to generate a reset. Input to the Inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the Inverting Oscillator amplifier.

XTAL1 XTAL2

ATmega162/V
2513JSAVR08/07

ATmega162/V
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
Note: 1.

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C.

7
2513JSAVR08/07

Register Summary
Address
(0xFF) .. (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61)

Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL Reserved Reserved ICR3H ICR3L Reserved Reserved ETIMSK ETIFR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCMSK1 PCMSK0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CLKPR

Bit 7
COM3A1 ICNC3

Bit 6
COM3A0 ICES3

Bit 5
COM3B1

Bit 4
COM3B0 WGM33

Bit 3
FOC3A WGM32

Bit 2
FOC3B CS32

Bit 1
WGM31 CS31

Bit 0
WGM30 CS30

Page

131 128 133 133 133 133 133 133

Timer/Counter3 Counter Register High Byte Timer/Counter3 Counter Register Low Byte Timer/Counter3 Output Compare Register A High Byte Timer/Counter3 Output Compare Register A Low Byte Timer/Counter3 Output Compare Register B High Byte Timer/Counter3 Output Compare Register B Low Byte

Timer/Counter3 Input Capture Register High Byte Timer/Counter3 Input Capture Register Low Byte PCINT15 PCINT7 CLKPCE PCINT14 PCINT6 TICIE3 ICF3 PCINT13 PCINT5 OCIE3A OCF3A PCINT12 PCINT4 OCIE3B OCF3B PCINT11 PCINT3 CLKPS3 TOIE3 TOV3 PCINT10 PCINT2 CLKPS2 PCINT9 PCINT1 CLKPS1 PCINT8 PCINT0 CLKPS0

134 134

135 135

88 88

41

ATmega162/V
2513JSAVR08/07

ATmega162/V
Address
(0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C)
(2) (2)

Name
Reserved SREG SPH SPL UBRR1H UCSR1C GICR GIFR TIMSK TIFR SPMCR EMCUCR MCUCR MCUCSR TCCR0 TCNT0 OCR0 SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL TCCR2 ASSR ICR1H ICR1L TCNT2 OCR2 WDTCR
(2)

Bit 7
I SP15 SP7 URSEL1 URSEL1 INT1 INTF1 TOIE1 TOV1 SPMIE SM0 SRE JTD FOC0

Bit 6
T SP14 SP6 UMSEL1 INT0 INTF0 OCIE1A OCF1A RWWSB SRL2 SRW10 WGM00

Bit 5
H SP13 SP5 UPM11 INT2 INTF2 OCIE1B OCF1B SRL1 SE SM2 COM01

Bit 4
S SP12 SP4 UPM10 PCIE1 PCIF1 OCIE2 OCF2 RWWSRE SRL0 SM1 JTRF COM00

Bit 3
V SP11 SP3 USBS1 PCIE0 PCIF0 TICIE1 ICF1 BLBSET SRW01 ISC11 WDRF WGM01

Bit 2
N SP10 SP2

Bit 1
Z SP9 SP1 UBRR1[11:8] UCSZ10 IVSEL TOIE0 TOV0 PGERS SRW11 ISC01 EXTRF CS01

Bit 0
C SP8 SP0 UCPOL1 IVCE OCIE0 OCF0 SPMEN ISC2 ISC00 PORF CS00

Page
10 13 13 190 189 61, 86 87 102, 134, 154 103, 135, 155 221 30,44,85 30,43,84 43,51,207 100 102 102

UCSZ11 TOIE2 TOV2 PGWRT SRW00 ISC10 BORF CS02

0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20
(2)

Timer/Counter0 (8 Bits) Timer/Counter0 Output Compare Register TSM COM1A1 ICNC1 XMBK COM1A0 ICES1 XMM2 COM1B1 XMM1 COM1B0 WGM13 XMM0 FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR310 WGM10 CS10

32,70,105,156 128 131 133 133 133 133 133 133

Timer/Counter1 Counter Register High Byte Timer/Counter1 Counter Register Low Byte Timer/Counter1 Output Compare Register A High Byte Timer/Counter1 Output Compare Register A Low Byte Timer/Counter1 Output Compare Register B High Byte Timer/Counter1 Output Compare Register B Low Byte FOC2 WGM20 COM21 COM20 WGM21 AS2 CS22 TCN2UB CS21 OCR2UB CS20 TCR2UB

149 152 134 134 151 151

Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Low Byte Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register URSEL0 URSEL0 UMSEL0 UPM01 WDCE UPM00 USBS0 WDE WDP2 UCSZ01 WDP1 UCSZ00 WDP0 UCPOL0 EEAR8 UBRR0[11:8]

53 190 189 20 20 21

(0x40)

UBRR0H UCSR0C EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR PORTE DDRE PINE OSCCAL OCDR UDR1 UCSR1A

0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04(1) (0x24)(1) 0x03 (0x23) 0x02 (0x22)

EEPROM Address Register Low Byte EEPROM Data Register PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC0 RXCIE0 ACD PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC0 TXCIE0 ACBG CAL6 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 DORD UDRE0 UDRIE0 ACO CAL5 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 MSTR FE0 RXEN0 ACI CAL4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 CPOL DOR0 TXEN0 ACIE CAL3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 CPHA UPE0 UCSZ02 ACIC PORTE2 DDE2 PINE2 CAL2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 SPR1 U2X0 RXB80 ACIS1 PORTE1 DDE1 PINE1 CAL1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM0 TXB80 ACIS0 PORTE0 DDE0 PINE0 CAL0

21 82 82 82 82 82 82 82 82 83 83 83 83 164 164 162 186 186 187 190 195 83 83 83 39 202 186

SPI Data Register

USART0 I/O Data Register

USART0 Baud Rate Register Low Byte

On-chip Debug Register USART1 I/O Data Register RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1

186

9
2513JSAVR08/07

Address
0x01 (0x21) 0x00 (0x20)

Name
UCSR1B UBRR1L

Bit 7
RXCIE1

Bit 6
TXCIE1

Bit 5
UDRIE1

Bit 4
RXEN1

Bit 3
TXEN1

Bit 2
UCSZ12

Bit 1
RXB81

Bit 0
TXB81

Page
187 190

USART1 Baud Rate Register Low Byte

Notes:

1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

10

ATmega162/V
2513JSAVR08/07

ATmega162/V
Instruction Set Summary
Mnemonics Operands Description Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd Rr Rd Rd K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF Rd Rd 0x00 Rd Rd Rd v K Rd Rd (0xFF - K) Rd Rd + 1 Rd Rd 1 Rd Rd Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers Ones Complement Twos Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2

1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1

PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd Rr Rd Rr C Rd K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1

R1:R0 (Rd x Rr) <<

BRANCH INSTRUCTIONS

11
2513JSAVR08/07

Mnemonics
BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH

Operands
k k Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, Z Rd, Z+ Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b

Description
Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG

Operation
if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1

Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H

#Clocks
1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DATA TRANSFER INSTRUCTIONS

BIT AND BIT-TEST INSTRUCTIONS

12

ATmega162/V
2513JSAVR08/07

ATmega162/V
Mnemonics
CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only None None None None 1 1 1 N/A

Operands

Description
Clear Half Carry Flag in SREG

Operation
H0 H

Flags

#Clocks
1

13
2513JSAVR08/07

Ordering Information
Speed (MHz) Power Supply Ordering Code ATmega162V-8AI ATmega162V-8PI ATmega162V-8MI ATmega162V-8AU(2) ATmega162V-8PU(2) ATmega162V-8MU(2) ATmega162-16AI ATmega162-16PI ATmega162-16MI ATmega162-16AU(2) ATmega162-16PU(2) ATmega162-16MU(2) Package(1) 44A 40P6 44M1 44A 40P6 44M1 44A 40P6 44M1 44A 40P6 44M1 Operation Range

8(3)

1.8 - 5.5V

Industrial (-40C to 85C)

16(4)

2.7 - 5.5V

Industrial (-40C to 85C)

Notes:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See Figure 113 on page 266. 4. See Figure 114 on page 266.

Package Type 44A 40P6 44M1 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40-pin, 0.600 Wide, Plastic Dual Inline Package (PDIP) 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (QFN/MLF)

14

ATmega162/V
2513JSAVR08/07

ATmega162/V
Packaging Information
44A

PIN 1 B
PIN 1 IDENTIFIER

E1

D1 D C

0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM 1.00 12.00 10.00 12.00 10.00 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE

A2

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.

E1 B C L e

10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B

15
2513JSAVR08/07

40P6

PIN 1

E1

SEATING PLANE

L B1 e E B

A1

C eB

0 ~ 15

REF
SYMBOL A A1 D E E1 B

COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM 2.540 TYP MAX 4.826 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE

Notes:

1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

B1 L C eB e

09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B

16

ATmega162/V
2513JSAVR08/07

ATmega162/V
44M1

Marked Pin# 1 ID

SEATING PLANE

TOP VIEW

A1 A3

K L D2
Pin #1 Corner

A
SIDE VIEW

1 2 3

Option A

Pin #1 Triangle

COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL

Option B
Pin #1 Chamfer (C 0.30)

E2

MIN 0.80

NOM 0.90 0.02 0.25 REF

MAX 1.00 0.05

NOTE

A A1 A3 b

0.18 6.90 5.00 6.90 5.00

0.23 7.00 5.20 7.00 5.20 0.50 BSC

0.30 7.10 5.40 7.10 5.40

K b e

Option C

D
Pin #1 Notch (0.20 R)

D2 E E2 e

BOTTOM VIEW

Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.

L K

0.59 0.20

0.64 0.26

0.69 0.41

5/27/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 44M1 REV. G

17
2513JSAVR08/07

Errata
ATmega162, all rev.

The revision letter in this section refers to the revision of the ATmega162 device. There are no errata for this revision of ATmega162. However, a proposal for solving problems regarding the JTAG instruction IDCODE is presented below. IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1. IDCODE masks data from TDI input The public but optional JTAG instruction IDCODE is not implemented correctly according to IEEE1149.1; a logic one is scanned into the shift register instead of the TDI input while shifting the Device ID Register. Hence, captured data from the preceding devices in the boundary scan chain are lost and replaced by all-ones, and data to succeeding devices are replaced by all-ones during Update-DR. If ATmega162 is the only device in the scan chain, the problem is not visible. Problem Fix / Workaround Select the Device ID Register of the ATmega162 (Either by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller) to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Note that data to succeeding devices cannot be entered during this scan, but data to preceding devices can. Issue the BYPASS instruction to the ATmega162 to select its Bypass Register while reading the Device ID Registers of preceding devices of the boundary scan chain. Never read data from succeeding devices in the boundary scan chain or upload data to the succeeding devices while the Device ID Register is selected for the ATmega162. Note that the IDCODE instruction is the default instruction selected by the Test-Logic-Reset state of the TAP-controller. Alternative Problem Fix / Workaround If the Device IDs of all devices in the boundary scan chain must be captured simultaneously (for instance if blind interrogation is used), the boundary scan chain can be connected in such way that the ATmega162 is the first device in the chain. Update-DR will still not work for the succeeding devices in the boundary scan chain as long as IDCODE is present in the JTAG Instruction Register, but the Device ID registered cannot be uploaded in any case. 2. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR.

18

ATmega162/V
2513JSAVR08/07

ATmega162/V
Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.

Changes from Rev. 1. Updated Features on page 1. 2513I-04/07 to Rev. 2. Added Data Retention on page 7. 2513J-08/07
3. Updated Errata on page 18. 4. Updated Version on page 205. 5. Updated C Code Example(1) on page 172. 6. Updated Figure 18 on page 35. 7. Updated Clock Distribution on page 35. 8. Updated SPI Serial Programming Algorithm on page 246. 9. Updated Slave Mode on page 162.

Changes from Rev. 1. Updated Using all 64KB Locations of External Memory on page 34. 2513H-04/06 to 2. Updated Bit 6 ACBG: Analog Comparator Bandgap Select on page 195. Rev. 2513I-04/07
3. Updated VOH conditions inDC Characteristics on page 264.

Changes from Rev. 1. Added Resources on page 7. 2513G-03/05 to 2. Updated Calibrated Internal RC Oscillator on page 38. Rev. 2513H-04/06
3. Updated note for Table 19 on page 50.

4. Updated Serial Peripheral Interface SPI on page 157.

Changes from Rev. 1. MLF-package alternative changed to Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF. 2513F-09/03 to Rev. 2513G-03/05
2. Updated Electrical Characteristics on page 264 3. Updated Ordering Information on page 14

Changes from Rev. 1. Removed Preliminary from the datasheet. 2513D-04/03 to 2. Added note on Figure 1 on page 2. Rev. 2513E-09/03
3. Renamed and updated On-chip Debug System to JTAG Interface and On-chip Debug System on page 46. 4. Updated Table 18 on page 48 and Table 19 on page 50.

19
2513JSAVR08/07

5. Updated Test Access Port TAP on page 197 regarding JTAGEN. 6. Updated description for the JTD bit on page 207. 7. Added note on JTAGEN in Table 99 on page 233. 8. Updated Absolute Maximum Ratings* and DC Characteristics in Electrical Characteristics on page 264. 9. Added a proposal for solving problems regarding the JTAG instruction IDCODE in Errata on page 18.

Changes from Rev. 1. Updated the Ordering Information on page 14 and Packaging Information on page 15. 2513C-09/02 to Rev. 2513D-04/03
2. Updated Features on page 1. 3. Added characterization plots under ATmega162 Typical Characteristics on page 275. 4. Added Chip Erase as a first step under Programming the Flash on page 260 and Programming the EEPROM on page 262. 5. Changed CAL7, the highest bit in the OSCCAL Register, to a reserved bit on page 39 and in Register Summary on page 8. 6. Changed CPCE to CLKPCE on page 41. 7. Corrected code examples on page 55. 8. Corrected OCn waveforms in Figure 52 on page 120. 9. Various minor Timer1 corrections. 10. Added note under Filling the Temporary Buffer (Page Loading) on page 224 about writing to the EEPROM during an SPM Page Load. 11. Added section EEPROM Write During Power-down Sleep Mode on page 24. 12. Added information about PWM symmetry for Timer0 on page 98 and Timer2 on page 147. 13. Updated Table 18 on page 48, Table 20 on page 50, Table 36 on page 77, Table 83 on page 205, Table 109 on page 247, Table 112 on page 267, and Table 113 on page 268. 14. Added Figures for Absolute Maximum Frequency as a function of VCC, ATmega162 on page 266. 15. Updated Figure 29 on page 64, Figure 32 on page 68, and Figure 88 on page 210. 16. Removed Table 114, External RC Oscillator, Typical Frequencies(1), on page 265. 17. Updated Electrical Characteristics on page 264.

20

ATmega162/V
2513JSAVR08/07

ATmega162/V
Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02 Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

1. Added information for ATmega162U. Information about ATmega162U included in Features on page 1, Table 19, BODLEVEL Fuse Coding, on page 50, and Ordering Information on page 14.

21
2513JSAVR08/07

Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600

International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581

Product Contact
Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts

Literature Requests www.atmel.com/literature

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2513JSAVR08/07