Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 20 views

    CS221: VHDL Introduction

    Uploaded by

    Megha Sharma
    - VHDL is a hardware description language used to model digital systems and chips. It allows specification of requirements, structure, behavior over time, and simulation. - A VHDL model consists of an entity defining the external interface and ports, and an architecture specifying the functionality. The architecture uses language constructs like processes for concurrency and types for bit-widths. - VHDL supports modeling essential aspects of hardware like timing through clocks, structure through blocks and wiring, and electrical characteristics like current levels and edge sensitivity.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    CS221: VHDL Introduction

    Uploaded by

    Megha Sharma
    20 views22 pages
    - VHDL is a hardware description language used to model digital systems and chips. It allows specification of requirements, structure, behavior over time, and simulation. - A VHDL model consists of an entity defining the external interface and ports, and an architecture specifying the functionality. The architecture uses language constructs like processes for concurrency and types for bit-widths. - VHDL supports modeling essential aspects of hardware like timing through clocks, structure through blocks and wiring, and electrical characteristics like current levels and edge sensitivity.

    Original Title

    Lec31

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    - VHDL is a hardware description language used to model digital systems and chips. It allows specification of requirements, structure, behavior over time, and simulation. - A VHDL model consists of an entity defining the external interface and ports, and an architecture specifying the functionality. The architecture uses language constructs like processes for concurrency and types for bit-widths. - VHDL supports modeling essential aspects of hardware like timing through clocks, structure through blocks and wiring, and electrical characteristics like current levels and edge sensitivity.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    20 views22 pages

    CS221: VHDL Introduction

    Uploaded by

    Megha Sharma
    - VHDL is a hardware description language used to model digital systems and chips. It allows specification of requirements, structure, behavior over time, and simulation. - A VHDL model consists of an entity defining the external interface and ports, and an architecture specifying the functionality. The architecture uses language constructs like processes for concurrency and types for bit-widths. - VHDL supports modeling essential aspects of hardware like timing through clocks, structure through blocks and wiring, and electrical characteristics like current levels and edge sensitivity.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 22

    CS221: VHDLIntroduction

    Dr.A.Sahu DeptofComp.Sc.&Engg. Dept of Comp. Sc. & Engg. IndianInstituteofTechnologyGuwahati


    1

    Outline
    ICDesignprocess WhatisVHDL h q RequirementofVHDL Model VHDL
    basiclanguageconcepts basicdesignmethodology examples
    2

    Hardware/SoftwareDesignFlow Hardware/Software Design Flow


    HW Specification Synthesis Layout Fabrication Fabrication IC Compilation Binary Code SW Specification

    ICDesignProcess IC Design Process


    Id Idea Layout Fabrication F b i ti Die Testing T ti Tested Die Packaging P k i

    Design D i

    Specification Implementation Model Synthesis Verification&Simulation

    VHDL
    VeryHardDifficultLanguage VHSICHardware DescriptionLanguage VHSIC VHSIC VeryHighSpeedIntegratedCircuits
    5

    ModelingDigitalSystems Modeling Digital Systems


    VHDLisforcodingmodelsofadigitalsystem... Reasonsformodeling
    requirementsspecification documentation d t ti testingusingsimulation formalverification formal verification synthesis

    Goal
    mostreliabledesignprocess,withminimumcostand time avoiddesignerrors!
    6

    VHDL
    VHDL is NOT C VHDLisNOTC... Therearesomesimilarities,aswithany programminglanguage,butsyntaxandlogic programming language but syntax and logic arequitedifferent;sogetoverit!!

    RequirementofanyHDL 1 Requirement of any HDL 1 Time


    howthebehaviour ofthesystem y changeswithtime creatingwaveforms f

    RequirementofanyHDL 2 Requirement of any HDL 2

    Periodic Signals PeriodicSignals


    clocks clocks

    RequirementofanyHDL 3 Requirement of any HDL 3 Concurrency


    x=x+1 y=a b

    P1 P2 Specify:ProcessesP1andP2 executeinparallel execute in parallel


    10

    RequirementofanyHDL 4 Requirement of any HDL 4 Structure,Compositionand p X Interconnection


    A X1 Y1 W B X2

    BlockAconsistsoftwoblocks:X1andY1 Block X is duplicated BlockXisduplicated WireWconnectsAandB

    11

    RequirementofanyHDL 5 Requirement of any HDL 5


    Bittrue data types Bit truedatatypes
    NotsoimportantinSW ImportantinHW I t t i HW

    int<6:0>var; Specify the bitwidth of variables Specifythebitwidthofvariables

    12

    RequirementofanyHDL 6 Requirement of any HDL 6

    Modules and Interfaces ModulesandInterfaces Ports


    InputPortP InputPortQ InputPortR outPortW Inout Port X PortX

    13

    RequirementofanyHDL 7 Requirement of any HDL 7


    Electrical Characteristics ElectricalCharacteristics
    CurrentLevels

    Tristating T i t ti y Sensitivity
    Risingedge/fallingedge

    14

    RequirementofanyHDL 8 Requirement of any HDL 8 Other programming constructs Otherprogrammingconstructs


    TextandFileI/O /

    usefulinsimulation/debugging

    15

    RequirementofanyHDL 9 Requirement of any HDL 9


    Bittrue data types Bit truedatatypes
    NotsoimportantinSW ImportantinHW I t t i HW

    int<6:0>var; Specify the bitwidth of variables Specifythebitwidthofvariables

    16

    RequirementofanyHDL 5 Requirement of any HDL 5


    Bittrue data types Bit truedatatypes
    NotsoimportantinSW ImportantinHW I t t i HW

    int<6:0>var; Specify the bitwidth of variables Specifythebitwidthofvariables

    17

    RequirementofanyHDL 5 Requirement of any HDL 5


    Bittrue data types Bit truedatatypes
    NotsoimportantinSW ImportantinHW I t t i HW

    int<6:0>var; Specify the bitwidth of variables Specifythebitwidthofvariables

    18

    FundamentalVHDLObjects Fundamental VHDL Objects


    Entity and Architecture Pair EntityandArchitecturePair
    Entity
    VHDLModel Consistsof TwoParts EntityRepresent y p ExternalInterface

    ArchRepresent Architecture Architecture Contents/Function ality

    19

    VHDL:Entity VHDL: Entity


    Entity : Represent External Interface Entity:RepresentExternalInterface
    A Y B
    ENTITYand_gate IS PORT(A:INBIT; PORT ( A IN BIT B:INBIT; Y:OUTBIT ); ENDand_gate;

    Model Name PortType Port Type Port P Direction 20

    Entityhas Interface:No y functionality

    PortName

    VHDL:Architecture,Specifying functionality f l
    ARCHITECTUREdata_flow O C C d fl OFand_gate IS d S BEGIN y<=aANDb; ENDdata_flow;

    Mayhavemultiplearchitecturesfor givenentity i i
    differentviews differentlevelsofdetail
    21

    22

    You might also like