University of Twente

Faculty of Electrical Engineering, Mathematics and Computer Science

VHDL tutorial
For internal use only

E. Molenkamp

August 2010

Contents
1 2 Introduction ........................................................................................................................ 3 Simulation with ModelSim ................................................................................................ 4 2.1 Analyse/Compile ........................................................................................................ 5 2.1.1 Simulate .............................................................................................................. 6 2.1.2 Script file with the stimuli .................................................................................. 8 2.1.3 Stimuli generation with VHDL .......................................................................... 8 2.1.3.1 Connect the test set with the design under verification ................................ 10 2.2 Simulation model ..................................................................................................... 11 Synthesis with Quartus II ................................................................................................. 13 3.1 Start Quartus II ......................................................................................................... 13 3.2 Create a new project ................................................................................................. 14 3.3 Top level of the design ............................................................................................. 17 3.4 Compile (=synthesize).............................................................................................. 17 3.5 RTL viewer/Technology Map Viewer ..................................................................... 19 Post simulation ................................................................................................................. 20 Constraint file ................................................................................................................... 22 Programming the LiveDesign Evaluation kit ................................................................... 23 Synthesis with Precision RTL .......................................................................................... 24 Alternative description ..................................................................................................... 27 Verification of a design via simulation ............................................................................ 28 9.1 Code coverage .......................................................................................................... 28 9.2 Assertion Based Verification ................................................................................... 30

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1 Introduction
VHDL is the hardware description language used in this course. It is one of the languages used in many companies in Europe. Many tools are available for simulation and synthesis. We have chosen a toolset that can also be installed at home (Windows only; See table 1). Home X University

VHDL simulation

ModelSim-Altera Includes post simulation libraries for Altera devices. QuestaSim Has the same features as ModelSim but also includes PSL. Altera post simulation libraries for the cyclone devices. Quartus II Precision RTL Is a technology independent synthesis tool.

VHDL Synthesis

X X

Table 1: tools used in the course

The tools to be used at home can be downloaded from:

https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp

A disadvantage is that probably newer versions will be available at the time you download the software. Hence, the tutorial may not be correct anymore at that time. We expect minor changes.

2 Simulation with ModelSim

figure 1ModelSim screen

ModelSim (and QuestaSim) starts with the window shown in figure 1. Note In case the localsand objects windows are not shown select them menu VIEW. The upper left window shows the libraries and the lower window (transcript) is used for entering commands and for reporting information to the user. You can dock (as shown above) and undock (a separate window) using the arrow in the upper right corner of a window. An analysed VHDL file is stored in a library. Library work is used to store your analysed VHDL designs. The first step is to create a library work: FileChange directory and browse to the directory that contain the design files. Enter the command: vlib work <return> Notes 1 The library work should be added in the workspace. If work does not appear in the workspace then close ModelSim and start it again and browse to the design directory. Now it is there! 2 The contents of the library work is managed by ModelSim. Never change the contents or place your source files in this library! The library work is created but is still empty. A correctly analysed design unit (entity, architecture, package, package body or configuration) is placed in library work. As an example a circuit that counts the number of ones in the input pattern is used in this tutorial.

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY count IS GENERIC (w : positive := 8); PORT (a : IN std_logic_vector(w-1 DOWNTO 0); q : OUT integer RANGE 0 TO w); END count; ARCHITECTURE behaviour OF count IS FUNCTION cnt (a:std_logic_vector) RETURN integer IS VARIABLE nmb : INTEGER RANGE 0 TO a'LENGTH; BEGIN nmb := 0; FOR i IN a'RANGE LOOP IF a(i)='1' THEN nmb:=nmb+1; END IF; END LOOP; RETURN nmb; END cnt; BEGIN q <= cnt(a); END behaviour;

Figure 2: behavioural description of count (the line numbers are not part off the VHDL code!)

The generic w, on line 4, is a global constant with value 8. The input a of this design is w bits wide. The output q is an integer value. The width of the input is w therefore the number of ones must be between 0 and w (inclusive). A range constraint is added to the integer type. The range constraint is not necessary but it can be used for documentation and will help synthesis. There are many ways to count the number of ones in an array. In the architecture (figure 2) a function is declared that takes care of this. This function has as input an object of type std_logic_vector. A std_logic_vector is an unconstrained array; the length of this type is not (yet) known! The reason to use an unconstrained array as input is to make the design generic with respect to the width of the input. At the location of the function call, line 20, the range of the input is known. The algorithm used in the function is straightforward. With a loop statement all elements of the inputs are examined. The only problem is: what are the vector indices? The attribute 'range is used for this. If the function is called with an object that is declared as std_logic_vector(5 to 36) then within the function the a'range is replaced with 5 to 36.

2.1 Analyse/Compile
Place a copy of the file count.vhd in the design directory. Via the menu compile you can compile this description. Compile the design via compilecompile.

Figure 3: the result after compilation

If there were no errors then your ModelSim environment should look like figure 3. In library work the entity and architecture of the design is located. In case of an error you can double click the error message and an editor is opened with your design on the line where the error was found.

2.1.1 Simulate
Click with the right mouse button on the architecture name behaviour and you can load your design in the simulator (or you can use menu simulatestart simulation).

Figure 3a: Selection of the design that should be simulated

Note: The free ModelSim-Altera edition does not allow optimizations. In case a licenced version of ModelSim/QuestaSim is used optimizations are possible. An optimization improves simulation speed but during debugging not all signals and variables are visible. Therefore chose full visibility in the tab Optimization Options. 6

During simulation you probably like to see some waveforms therefore enter: add wave * <return>1 (In stead of * you may enter a list with the signal names separated with a comma). Note If the signals a and q are not shown in the Wave window then you probably did not select count in the workspace/instance window. Select count and repeat the command.

Figure 3b: Selection of the design that should be simulated

With the run command you perform a simulation: run 200ns <enter> Why are the inputs values U? With the force command you can apply an input pattern to a: force a 01100011 <enter> run 100ns<enter> Try it with some other values for a. You can assign multiple values to the input with: force a 11111111, 00111111 10ns, 11110101 20ns Try it.
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You can also drag and drop from the objects and locals windows in the wave window. The locals window shows the variables and the objects window contains the signals that are visible at the selection in the workspace/instance window.

2.1.2 Script file with the stimuli

A tool dependent solution to apply stimuli is to use a script file. A simple example is given beneath. Create a file demo.do with the following contents: force a 00011111 run 100ns force a 10100000 run 100ns In ModelSim this script file is executed with the command: do demo.do <return> Notes 1 In a synchronous design a clock signal is needed. Assume signal clk is the clock line. A repetitive pattern is created with the command: force clk 0, 1 50 ns repeat 100ns 2 The ModelSim command run all performs a simulation and will stop when nothing is scheduled for the future. Do not use this command when a clock signal is generated with the method described in Note 1. Why not? Commands that are entered in the transcript window can be written to a file with the command: write transcript < filename>. This file can be used as a script file.

2.1.3 Stimuli generation with VHDL

Applying stimuli as presented in the previous section is tool dependent. You can also use VHDL to generate stimuli. Finding test data for a design is not an easy task. In this chapter we only illustrate that stimuli can be generated.
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY testset IS GENERIC (w : positive := 8); PORT (data : OUT std_logic_vector(w-1 DOWNTO 0)); END testset; ARCHITECTURE set1 OF testset IS BEGIN PROCESS BEGIN data <= (others => '0'); -- all zero WAIT FOR 10 ns; data <= (others => '1'); WAIT FOR 10 ns; -- all one

FOR i IN 0 to 2**w-1 LOOP data <= std_logic_vector(to_unsigned(i,w)); EXIT WHEN i=20; -- an exhaustive test is not performed if w is large WAIT FOR 10 ns; END LOOP; WAIT; -- forever END PROCESS; END set1;

Figure 4: simple test set.

Figure 4 shows a simple test set. It contains one process statement. It first generates all zeros, waits for 10 ns, then generates all ones and it waits again, Of course an exhaustive test is possible. In the for-statement the loop variable i (which is implicitly declared!) goes from 0 to 8

2w-1. This integer value is converted to a bit pattern (using a binary coding; also called unsigned). For the conversion the function to_unsigned is used. This function converts the integer value i to a binary vector with length w. This function is located in a package numeric_std (in library ieee). However in case the generic (~ constant) w is large this is a time consuming task. Therefore in this example the loop is ended in case i is equal to 20. The process ends with wait. This means the process will not resume execution.

Background information: numeric_std The package numeric_std declares two types: - signed (twos complement representation) and - unsigned (binary representation). Both types are similar to type std_logic_vector; arrays with elements of type std_logic
variable sa,sb,sc : signed(2 downto 0); variable ua,ub,uc : unsigned(2 downto 0); variable a,b,c : std_logic_vector(2 downto 0);

If sa is 111 then it is interpreted as -1 (twos complement). If ua is 111 then it is interpreted as 7. Is a is 111 then no number interpretation is associated with it! What is the result of the statement: sa := sb + 11 ? The operands do not have the same length. Since sb is of type signed the shortest vector is sign extended before the addition takes places. In case the operands are of type unsigned the shortest vector is extended with zeros. In case the operands are of type std_logic_vector you cannot perform an addition because no number interpretation is associated with this type. VHDL is a strongly typed language therefore you can not write:
a := sa;

However the types are closely related. In that case a type conversion function can be used:
a := std_logic_vector(sa);

If you want the integer value of a vector you simply write:

integer_value := to_integer(sa);

If you want to convert an integer to a vector you must add the length of the vector:
sa := to_signed(integer_value,3) or us := to_unsigned(integer_value,3)

If the simulator is still active, end the current simulation via the simulate menu. Compile the file testset.vhd and simulate the design entity testset. Figure 5 shows the simulation result. The test pattern generation will end at the wait statement. If you enter run all <enter> the simulator simulates until no signal changes are planned for the future. Be careful with this command. If you use the following concurrent statement to generate a clock clk <= not clk after 10 ns; simulation will never end.

Figure 5: simulation result of the test set

2.1.3.1 Connect the test set with the design under verification
Figure 6 shows the structural VHDL description that connects the design entity testset with design entity count. Compile file testbench.vhd and simulate entity testbench. Check that the length of the pattern is changed to 10 in the design!
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY testbench IS GENERIC (width : positive := 10); END testbench; ARCHITECTURE structure OF testbench IS COMPONENT testset GENERIC (w : positive := 8); PORT (data : OUT std_logic_vector(w-1 DOWNTO 0)); END COMPONENT; COMPONENT count GENERIC (w : positive := 8); PORT (a : IN std_logic_vector(w-1 DOWNTO 0); q : OUT integer RANGE 0 TO w); END COMPONENT; -- local connections SIGNAL stimuli : std_logic_vector(width-1 DOWNTO 0); SIGNAL output : integer; BEGIN ts : testset GENERIC MAP (w => width) PORT MAP ( data => stimuli); dut : count GENERIC MAP (w => width) PORT MAP ( a => stimuli, q => output); END structure;

Figure 6: test bench

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Figure 7:The design hierarchy is shown in the upper left window

Via the buttons you can step through your design (e.g. to locate errors). The step button is often used. Then only one statement (concurrent or sequential) is executed. Also a source window is opened so you can see (the arrow) what the next statement to execute will be. Step -Over is similar to the execution of a function/procedure in one step. During debugging you often like to run your program to a certain point and perform a low level debugging from that point. Double click on the right of the line number of an executable line and a breakpoint appears.

Figure 8:Simulation result

2.2 Simulation model

VHDL is a collection of concurrent statements. The order of the concurrent statements has no effect on the behaviour. Processes can only communicate with each other using signals (I forget here the shared variable; dont use shared variables). If you assign a value to a signal that signal value is not updated immediately. This means that all processes will use the same signal values; consequently the simulation is order independent. If you assign a value to a variable that variable is updated immediately.

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Sometimes you are surprised by the update mechanism of signals. If you write:
y <= a after 10 ns;

The output y follows the input a with a delay of 10 ns. (More precise the input should be stable for 10 ns too.) If you write:
y <= a;

The output is updated after a delta delay. Delta delays are not shown in the wave window. There can be infinite delta delays before simulation time advances. You will experience this if you dont see any progress during simulation but your simulation is still going on (for hours ). ModelSim will report a warning when it has executed 1000 delta steps. ModelSim also makes is possible to show the simulation results after every delta steps. Repeat the previous simulation but (also) use the following command: add list * <return> Check that you really understand what is going on.

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3 Synthesis with Quartus II

With QuartusII a VHDL description is synthesized for Altera devices. Notes 1 Although not required for VHDL it is wise that the name of the file is the same of the name of the entity. 2 In the VHDL description the pin location of an input and output is not specified (although it is possible). Most synthesis tools do not handle the sensitivity list correctly. The synthesis tool assumes that the sensitivity list includes all signals read in the process. A mismatch between simulation and synthesis can occur if the process does not model synchronous hardware. ModelSim has an option (CompileCompile Options, and then check for synthesis). With this option the compiler will check for incomplete sensitivity lists.

The constraint file (with the file extension: qsf) should be in the same directory as the design. De constraint file contains the pin locations of the input and output signals. If no constraint file is added the software maps an input and output to a pin. For now will skip the constraint file (see chapter 5). The constraint file should be in the directory before you start Quartus.

3.1 Start Quartus II

Note

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The first time you start Quartus you can choose between QuartusII or MaxPlus look and feel. Choose: Quartus. Next you are asked if you have purchased an IP library, which is probably not the case, so choose: run the Quartus II software.

3.2 Create a new project

FileNew Project Wizard Browse to the directory use as name for the project: count

Next

Select the file(s) you want to include: count.vhd. Dont forget to click on the add button afterwards!

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Next

Choose technology Cyclone and device EP1C12F324C8. This depends on the FPGA on the board used.

Simulation Tool name: ModelSim-Altera and Format: VHDL This allows post simulation of the design. This will be discussed in chapter 4. Next

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Finish.

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3.3 Top level of the design

The picture above is from another design With the mouse right click on the file that contains the top level of the design. Now you can set it as top level.

3.4 Compile (=synthesize)

ProcessingStart Compilation Note Only a subset of VHDL is synthesizable therefore it is possible that Quartus, and other synthesis tools, generate error messages!

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3.5 RTL viewer/Technology Map Viewer

After synthesis a schematic can be generated: - RTL view; this view is very close to the VHDL description. - Technology view is an optimized result for the technology. ToolsNetlist ViewersRTL Viewer

ToolsNetlist ViewersTechnology Map Viewer

Notice that the loop structure in the VHDL description is visible in the RTL view whereas in the Technology Map view it is realized with an efficient tree like implementation.

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4 Post simulation
After synthesis a post simulation can be performed with the the real delays (as expected by Quartus for the given device). During simulation several constraint are checked like setup and hold times. In the project directory the following directory is created: simulation\modelsim In this directory there are the files: - count.vho (VHDL output file) - count_vhd.sdo (standard delay output file) Note: The extension, and names, of these files depends on the synthesis tool. A fragment of the generated VHDL file is:
--- Device: Altera EP1C12F324C8 Package FBGA324 ---- This VHDL file should be used for ModelSim-Altera (VHDL) only -LIBRARY IEEE, cyclone; USE IEEE.std_logic_1164.all; USE cyclone.cyclone_components.all; ENTITY count IS PORT ( a : IN std_logic_vector(7 DOWNTO 0); q : OUT std_logic_vector(3 DOWNTO 0) ); END count;

Notice that the entity description is different from the original description (see figure 2). The generic value is synthesized and used for the output Q. The integer range 0 to 8 is synthesized with a std_logic_vector(3 DOWNTO 0). Furthermore technology specific libraries are used. ModelSim-Altera includes the precompiled libraries. Note: For the QuestaSim version installed on de lab machines pre-compiled libraries for the Cyclone devices are available. To perform a post simulation the following steps are required: 1. Filechange directory go to ..\simulation\modelsim 2. create a work library (vlib work) 3. compile count.vho (vcom count.vho)

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4. simulatestart simulation

a. Tab design: Select your design and set the resolution to ps (The delays in the SDF files is in pico seconds). b. Tab SDF Voeg de count_vhd.sdo file toe (via ADD) Note 1: For QuestaSim, installed on de lab machines, set enable optimization! Note 2: You can also apply a region. This is required in case the synthesized design is part of a larger system (via a component instantiation). The path to the component is the region (e.g. if it is instantiated in the top-level architecture the label of the component instantiation is used).

5. Perform a simulation. Note: The default run lenght is now 100 ps. The default run length can be any other value. Therefore explicit add the unit in a script file; e.g. run 100ns in stead of run 100.

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5 Constraint file
In the top-level entity description the input and output ports are enumerated. However to which physical pin a port is connected has to be specified. This can be done in a constraint file. An example of a constraint file for Quartus is:.
set_location_assignment PIN_E16 -to q[0] set_location_assignment PIN_G14 -to q[1]

fragment of constraint file count.qsf For Quartus the name of the constraint file should be the same as the name of the top-level entity. The file should be located in the design directory. Notes 1 During synthesis Quartus will change the contents of the qsf file. Your constraint file should be in the design directory before you start Quartus.

Precision RTL (see chapter 7), and other tools, can use a SDC (Synopsys Design Constraint) file for the pin mapping. Precision RTL requires that the sdc file is explicitly included. The syntax is a little bit different: set_attribute -name pin_number -value E16 -port q(0) set_attribute -name pin_number -value G14 -port q(1)

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6 Programming the LiveDesign Evaluation kit

Note The constraint file with the pin mapping is required! To program the device perform the following steps: 1. Connect the programming cable to the parallel port of the PC 2. Connect the power supply 3. Program the device: ToolsProgammer and select the file count.sof. Select program/Configure. Next: start.

Notes 1 Probably the first time No hardware is detected. Click on Hardware Setup and select ByteblasterMV. 2 Sometimes the JTAG interface of the LiveDesign kit, used to program the device, can not be found. Solution: disconnect and connect the power supply of the board.

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7 Synthesis with Precision RTL

Notes For our lab we do not need Precision RTL. However the generated schematics are pleasant. Precision RTL is a technology independent synthesis tool. It can be used on top of Quartus (for Altera devices), or ISE (for Xilinx devices), etc.. It also can perform retiming: moving flip-flops in the design to increase the maximum clock frequency. Start Precision RTL.

Figure 8: Precision start up screen Click on new Project and browse to the folder that contains the source files (file count.vhd).) (the project name is not important, and create impl(ementation) should be selected (default)).

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Figure 9: Precision Desing tab Setup Design (target device) Click Setup Design and select device: AlteraCyclonedevice=EP1C12F324C, speed Grade=8 (other settings or not important for the lab). Press OK. Input files Click Add Input Files. Note The order is not important. The tool automatically reorders the files. Select the design files and press OK. Compile the design Press the compile button. The tab Design analysis is added to the lower left corner. Select this tab, and choose View RTL Schematic (figure 10).

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Figure 10:schematic view of the design Notice that the schematic bundles the lines with the same name. In case an unbundled view is preffered: ToolsSet OptionsSchematic Viewer and deselect show bundled Instances and/or Show Net buses.

Figure 11:schematic view of the design with unbundled nets.

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8 Alternative description
The behavioral description of count (file count.vhd) was a straightforward and readable description. This description can be handed over to someone and probably (s)he will recognize the intention quite fast. Synthesis tools nowadays support these kinds of descriptions, and often find smart implementations. The tree like implementation is used by the synthesis tool because it knows the properties of the plus operation (associative and commutative). In case the tool does not use these properties you can force the tree like structure using q recursive description (figure 12).
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY count IS GENERIC (w : positive := 8); PORT (a : IN std_logic_vector(w-1 DOWNTO 0); q : OUT integer); END count; ARCHITECTURE recursive OF count IS -- count bit with a balanced tree approach FUNCTION count_bits(vec: std_logic_vector) RETURN integer IS CONSTANT n: natural := vec'LENGTH; CONSTANT v: std_logic_vector(1 TO n) := vec; BEGIN CASE n IS WHEN 0 => RETURN 0; WHEN 1 => IF v(1) = '1' THEN RETURN 1; ELSE RETURN 0; END IF; WHEN OTHERS => RETURN count_bits(v(1 to n/2)) -- 2 + count_bits(v(n/2+1 to n)); END CASE; END count_bits; BEGIN q <= count_bits(a); END recursive;

Figure 12: recursion (file count_recursive_funct2.vhd) Remember the function count_bits, figure 12, has as input a std_logic_vector. This is an unconstrained array. Not only the length but also the left and right index is not known. Therefore the two constant declarations are used. Synthesize this design and have a look at the RTL schematic.

The division operator, with integer types, will always give an integer result. Hence 8/3 is 2.66666 and the integer result is 2.

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9 Verification of a design via simulation

Simulation tools often have features to ease the verification of the design, e.g.: - Code coverage - Assertion based verification

9.1 Code coverage

QuestaSim supports several type of code coverages, e.g. statement coverage, branch coverage, condition coverage etc. A detailed description of the code coverage features is found in chapter 17 (HelpQuesta SV/AFV PDF Bookcase Questa SV/AFV users manual (QuestaSim version 6.5b)). This chapter only illustrates code coverage with the counter example. We are interested in all type of code coverages in the design count so we add +cover when compiling the design. I.e. for our counter example perform the following commands: vcom count_recursive_funct2.vhd +cover vcom testset.vhd vcom testbench.vhd Start simulation with code coverage: Start simulation tab Others enable checkbox code coverage tab Design and select entity testbench

Note: In a script code coverage can be enabled adding -coverage, e.g. vsim -coverage testbench Next: double click on dut and the missed type of coverages are shown (see figure 13).

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Figure 13: result of code coverage at the start of the simulation Note 1: If you point an X an explanation is shown.

Since no stimuli is applied yet all statements are missed. Simulate for 30 ns. Notice that the case when 0 is never executed. Can you explain this?

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Figure 14: Code coverage numbers. Notes 1 It is also possible to show the number of occurrences that a statement/condition is executed. ToolsCode CoverageShow Coverage Numbers (the window with the source file should be selected. See figure 14). 2 3 It is also possible to generate a report file: ToolsCoverage report.. The collected coverage data can be deleted: ToolsCode Coverageclear data (e.g. after a restart of the simulation)

9.2 Assertion Based Verification

A separate exercise in a couple of weeks.

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