Modified Booth Multiplier

Digital Electronics Fall 2008 Project 2

Booth Multiplier: an Introduction

Recode each 1 in multiplier as +2-1
Converts sequences of 1 to 100(-1) Might reduce the number of 1s
0 0 1 1 1 1 1 1 0 0

+1 0 1

+1 -1 0

+1 -1

+1 -1

+1 -1

+1 -1

-1

-1

Spring 2006

EE 5324 - VLSI Design II - Kia Bazargan

Booth Multiplier: Recoding (Encoding) Example

0 1 1 0 1 1 1 0 0 0 1 0

(+1 -1) (+1 -1)

(+1 -1) (+1 -1) (+1 -1)

0 -1 0

(+1 -1)

+1 0 -1 +1 0

0 +1 -1 0

If you use the last row in multiplication, you should get exactly the same result as using the first row (after all, they represent the same number!)
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Booth Recoding: Multiplication Example

Sign extension

0 0 0 0 0 0 0
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1 1 0 0 1 1

0 0 +1 0 1 0 0 1 0

0 1 0 0 0 0 0 0 1

1 1 0 0 1 0

1 1 -1 0 0

0 0 0 0

6x 14

(-6)

0 1 0 0

84
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EE 5324 - VLSI Design II - Kia Bazargan

Booth Recoding: Advantages and Disadvantages

Depends on the architecture
Potential advantage: might reduce the # of 1s in multiplier

In the multipliers that we have seen so far:

Doesnt save in speed (still have to wait for the critical path, e.g., the shift-add delay in sequential multiplier) Increases area: recoding circuitry AND subtraction

Spring 2006

EE 5324 - VLSI Design II - Kia Bazargan

Modified Booth
Booth 2 modified to produce at most n/2+1 partial products. Algorithm: (for unsigned numbers)
1. Pad the LSB with one zero. 2. Pad the MSB with 2 zeros if n is even and 1 zero if n is odd. 3. Divide the multiplier into overlapping groups of 3-bits. 4. Determine partial product scale factor from modified booth 2 encoding table. 5. Compute the Multiplicand Multiples 6. Sum Partial Products

Modified Booth Multiplier: Idea (cont.)

Can encode the digits by looking at three bits at a time Booth recoding table:
i+1
0 0 0 0 1 1 1 1
Spring 2006

i
0 0 1 1 0 0 1 1

i-1
0 1 0 1 0 1 0 1

add
0*M 1*M 1*M 2*M 2*M 1*M 1*M 0*M

Must be able to add multiplicand times 2, -1, 0, 1 and 2 Since Booth recoding got rid of 3s, generating partial products is not that hard (shifting and negating)

[Hauck]
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EE 5324 - VLSI Design II - Kia Bazargan

Modified Booth
Example: (n=4-bits unsigned) 1. Pad LSB with 1 zero
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0

2. n is even then pad the MSB with two zeros

0 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0

3. Form 3-bit overlapping groups for n=8 we have 5 groups

0 0 0 0 0 0 0 1 0 1 0 0 0 0

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

Modified Booth
4. Determine partial product scale factor from modified booth 2 encoding table.
0 0 0 0 0 1 0 1 0 0 0 Xi+1 0 0 Groups 0 0 0 Coding 0Y 0 0 1 1 1 1 Xi 0 0 1 1 0 0 1 1 Xi-1 0 1 0 1 0 1 0 1 Action 0Y 1Y 1Y 2Y -2 Y -1 Y -1 Y 0Y

0
0 0 0

1
1 0 0

0
0 0 0

1Y
1Y 0Y 0Y

Modified Booth
5. Compute the Multiplicand Multiples
0 0 0 0 0 1 0 0 0 Groups 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Coding 0Y 1Y 1Y 0Y 0Y 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 20 1Y 1Y 0Y 0Y

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Y

0 0 0 0 0 0 0 0

Compute Partial Products

0 Yi-1 Adders Yi

Xi+1
0 0

Xi
0 0

Xi-1
0 1

Action
0Y 1Y

0
0 1 1 1 1

1
1 0 0 1 1

0
1 0 1 0 1

1Y
2Y -2 Y -1 Y -1 Y 0Y

Xi-1 Xi Xi+1

Modified Booth
6. Sum Partial Products
0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 + 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 20 1Y 1Y

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Y

0Y 0Y

0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 160

Modified Booth
Booth 2 modified to produce at most n/2+1 partial products. Algorithm: (for unsigned numbers)
1. Pad the LSB with one zero. 2. If n is even dont pad the MSB ( n/2 PPs) and if n is odd sign extend the MSB by 1 bit ( n+1/2 PPs). 3. Divide the multiplier into overlapping groups of 3-bits. 4. Determine partial product scale factor from modified booth 2 encoding table. 5. Compute the Multiplicand Multiples 6. Sum Partial Products

Modified Booth
Example: (n=4-bits unsigned) 1. Pad LSB with 1 zero
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0

2. n is even then do not pad the MSB

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0

3. Form 3-bit overlapping groups for n=8 we have 5 groups

0 1 1 0 1 0 0 1 0 0

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

Modified Booth
4. Determine partial product scale factor from modified booth 2 encoding table.
0 1 1 0 1 0 0 1 0 Xi+1 0 0 Groups 0 1 1 0 0 0 Coding 1Y -2 Y 0 0 1 1 1 1 Xi 0 0 1 1 0 0 1 1 Xi-1 0 1 0 1 0 1 0 1 Action 0Y 1Y 1Y 2Y -2 Y -1 Y -1 Y 0Y

1 0

0 1

1 1

-1 Y 2Y

Modified Booth
5. Compute the Multiplicand Multiples
1 0 0 1 0 1 0 1 Groups 0 1 1 0 1 0 0 1 0 0 1 1 Coding 1Y -2 Y -1 Y 2Y 0 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 -107 105 1Y -2 Y -1 Y 2Y

1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1 -11235

Modified Booth Multiplier: Idea (cont.)

Interpretation of the Booth recoding table:
i+1 0 0 0 0 1 1 1 1
Spring 2006

i 0 0 1 1 0 0 1 1

i-1 0 1 0 1 0 1 0 1

add 0*M 1*M 1*M 2*M 2*M 1*M 1*M 0*M

Explanation No string of 1s in sight End of a string of 1s Isolated 1 End of a string of 1s Beginning of a string of 1s End one string, begin new one Beginning of a string of 1s Continuation of string of 1s
[Par] p. 160
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EE 5324 - VLSI Design II - Kia Bazargan

Modified Booth Recoding: Summary

Grouping multiplier bits into pairs
Orthogonal idea to the Booth recoding Reduces the num of partial products to half If Booth recoding not used have to be able to multiply by 3 (hard: shift+add)

Applying the grouping idea to Booth Modified Booth Recoding (Encoding)

We already got rid of sequences of 1s no mult by 3 Just negate, shift once or twice
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Modified Booth Multiplier: Summary (cont.)

Uses high-radix to reduce number of intermediate addition operands
Can go higher: radix-8, radix-16 Radix-8 should implement *3, *-3, *4, *-4 Recoding and partial product generation becomes more complex

Can automatically take care of signed multiplication

(we will see why)
Spring 2006 EE 5324 - VLSI Design II - Kia Bazargan 19