Module 5 PDF

MODULE-5
• Ports and Modules

• Lexical Conventions
• Data Types
• Operators
VERILOG HDL
CODING STYLE • Gate Level Modeling
• Data Flow Modeling
• Behavioral level Modeling
• Test Bench
MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 2

INTRODUCTION TO HDL
 The sequential model used in traditional programming
languages (i.e. “C”) cannot capture the characteristics of
digital hardware, and there is a need for special languages
(i.e., HDLs) that are designed to model digital hardware.
 The fundamental characteristics of a digital system are

defined by the concepts of entity, connectivity,
concurrency and timing.
 HDL is a language used to describe digital system.
 The goal of an HDL is to describe and model digital

systems faithfully and accurately.
INTRODUCTION TO HDL
 A hardware description language looks much like a
programming language such as C.
 Different HDLs are available different purpose such as

Analog system design , digital system design, PCB design.
 The two main HDLs are Verilog and VHDL for digital
system design.
 There are other, limited capability, languages such as

ABEL, CUPL, and PALASM that are tailored specifically
for PALs and CPLDs.
INTRODUCTION TO VERILOG HDL
 VERILOG HDL – VERIfiable LOGic HDL: Programming
language used to describe digital circuits and systems
 It is most commonly used in the design and verification

of digital circuits at the register-transfer
level of abstraction.
 It is also used in the verification of analog

circuits and mixed-signal circuits.
 One of the two most common HDL used by IC designers

(another one is VHDL)
INTRODUCTIONTO VERILOG HDL
 Similar to C/Pascal programming language
 Verilog Modeling ranges from Gate to Processor level and

it provides flexibility for creating used defined primitives
 In-build primitive logic gates (AND, OR, NAND etc) and

switch-level primitive gates (nmos, pmos, cmos etc)
 Verilog versions: Verilog-95, 2001, 2005, System Verilog

2009, 2012
 Verilog is case-sensitive and its file extension is .v

INTRODUCTIONTO VERILOG HDL
Verilog HDL Simulators
Commercial: Open sources: Online:
Xilinx ISE Verilator, iverilog.com,
Active HDL Icarus verilog, EDAPlaygro
Model sim GPL cver, und.com,
Quartus-II VeriWell Tarang EDA
MP Sim

VERILOG vs VHDL
VERILOG HDL VHDL
VERIfiable LOGarithmic HDL Very high speed integrated circuit HDL
Developed based on C-language Developed based on ADA-language
Easy to learn and understand Difficult to learn and understand
Case sensitive No case sensitive
It allows switch-level modelling switch-level modelling is not possible
Very simple data types Complex data types

All signals are initialized to “unknown” All signals are initialized to “zero” state, so
state to all allow the designer to initialize designer may omit the global reset
their logic

STRUCTURE OF VERILOG HDL

A SIMPLE VERILOG PROGRAM
 Verilog Code
// A simple example comment line
module and2 (a, b ,c); module name  Circuit

port list
input a, b;
port declarations a
c
output c; b
assign c = a & b; body
endmodule end module

MODULE
 Modules are the basic building blocks in Verilog. A
module definition starts with the keyword module ends
with the keyword endmodule
 Elements in a module module name (port_list)
port declarations
— Interface: consisting of port and parameter declarations
parameter declarations
ìnclude directives
— optional add-ons
variable declarations
assignments
— body: specification of internal low-level module instantiation
part of the module initial and always blocks
task and function
endmodule
MODULE - EXAMPLE
• General definition  Example

module HalfAdder (A, B, Sum Carry);
module module_name ( port_list );
input A, B;
port declarations;
output Sum, Carry;
…
assign Sum = A ^ B;
variable declaration;
//^ denotes XOR
…
assign Carry = A & B;
description of behavior
// & denotes AND
endmodule
endmodule

PORTS
 Port provides interface, through which module can
communicate its environment
 Port connecting rules: inputs, outputs, inouts, width
matching, unconnected ports
 All ports in the <port_list> must be declared in module.
Ports can be declared as,

PORTS - EXAMPLE
 Verilog Code  Circuit
module MAT (enable, data, all_zero, result, status);

input enable; // scalar input
input [3:0] data; // vector input all_zero
enable
output all_zero; // scalar output MAT result[2:0]
output [2:0] result; // vector output data[3:0] status[1:0]
Inout [1:0] status // bi-directional port
…… LSB MSB
endmodule
 To make code easy to read, use self-explanatory port names
 For the purpose of conciseness, use short port names
 In vector port declaration, MSB can be smaller index.

e.g. output [0:3] result (result[0] is the MSB)

LEXICAL CONVENTIONS
 Very similar to C
– Verilog is case-sensitive
– All keywords are in lowercase
– A Verilog program is a string of tokens
• Identifiers
• Escape Identifiers
• Keywords
• Comments
• Value Set
• Numbers
• Whitespace
• Strings

LEXICAL CONVENTIONS
IDENTIFIERS
 Identifiers are name given to objects so that they can be
referenced in the design
 Formed from {[A-Z], [a-z], [0-9], _, $}, but ..
 .. can’t begin with $ or [0-9]
– myidentifier valid
– m_y_identifier valid
– 3my_identifier invalid
– $my_identifier invalid
– _myidentifier$ valid
 Case sensitivity
myid  Myid

LEXICAL CONVENTIONS
ESCAPE IDENTIFIERS
 It provides the way of including any of the printable ASCII
characteristics in an identifiers
 It begin with back slash (\) and end with white space
 Some of examples are

\a*b*c
\**print value**
\4000
 An escaped keyword is not treated as same as the keyword
 The identifier \ begin is distinct from the identifier begin

myname  \myname
LEXICAL CONVENTIONS
KEYWORDS
 Keywords are predefined, special identifiers that define the
language constructs
 All key words defined in lower case
 Some of them are
input, output, inout
reg, wire, task, tri, time,
pmos, nmos, and, or, not, wor, xnor,
begin, parameter, buf, edge, join, medium,wait, use
if,else, case,while, always, initial, posedge, negedge, assign
end, endtask, endcase, endfunction, default, endtable,
endmodule
LEXICAL CONVENTIONS
COMMENTS
//The rest of the line is a comment
A= x^y; // this is single line comment
/* Multiple line comment*/

/* this is example of multiline comment
A= x^y;
C=a+b; */
/* Nesting /* comments */ do NOT work */

LEXICAL CONVENTIONS
VALUE SET
represents low logic level or false condition
represents high logic level or true condition
represents unknown logic level
represents high impedance logic level

LEXICAL CONVENTIONS
NUMBERS
 Number Specification
 Sized numbers
 Unsized numbers
 Unknown and high-impedance values
 Negative numbers
• Underscore character and question marks

– Use ‘_’ to improve readability
• 12’b1111_0000_1010
• Not allowed as the first character
– ‘?’ is the same as ‘z’ (only regarding numbers)
• 4’b10?? // the same as 4’b10zz
LEXICAL CONVENTIONS
NUMBERS
• Sized numbers
– General syntax: <size>’<base><number>
• <size> number of bits (in decimal), not the
number of hex or decimal digits
• <number> is the number in radix <base>
• <base> :
– d or D for decimal (radix 10)
– b or B for binary (radix 2)
– o or O for octal (radix 8)
– h or H for hexadecimal (radix 16)
• Examples:
– 4’b1111, 12’habc, 8’d255
LEXICAL CONVENTIONS
NUMBERS
 Unsized numbers
 Default base is decimal
 Default size is at least 32 (depends on Verilog compiler)
 Examples
 23232
 ’habc
 ’o234
 Negative numbers
 Put the sign before the <size>
 Examples:
 -6’d35
 4’d-12 // illegal

LEXICAL CONVENTIONS
NUMBERS
 X or Z values
– Unknown value: lowercase x or Uppercase X
• 4 bits in hex, 3 bits in octal, 1 bit in binary
– High-impedance value: lowercase z or Uppercase Z
• 4 bits in hex, 3 bits in octal, 1 bit in binary
– Examples
• 12’h13x
• 4’hX
• 32’bz
– Extending the most-significant part

– MS bit = 0, x or z  extend this
– 4’b x1 = 4’b xx_x1
– MS bit = 1  zero extension
– 4’b 1x = 4’b 00_1x
LEXICAL CONVENTIONS
WHITE SPACE & STRINGS
 Whitespace
 Blank space (\b)
 Tab (\t)
 Newline (\n)
 Strings
 As in C, use double-quotes
 Examples:
 “Hello world!”
 “a / b”
 “text\tcolumn1\bcolumn2\n”

DATA TYPES
NET
 Two groups of data types:
 Net: it represents connection between hardware elements
 Registers: represents an abstract data storage element
 Syntax for net declaration:

<net_list> [msb:lsb] net 1, net 2,……….net n;
 <net list> one of the net type
 [msb:lsb] specify ranges of the net
 Net is a value determined from the value of its drivers
 Nets are one-bit value unless they are declared as vectors and
default value of net is Z
Examples: wire a; wire b, c; wire d=1’b0;
DATA TYPES
NET TYPES
 A net declaration starts with keyword wire addr
……
Processor
Memory
wire r_w; // scalar signal data
wire [7:0] data; // vector signal
wire [9:0] addr; // vector signal r_w
……
 Different kinds of net data types are:
(A) Wire & tri-nets

(B) Wor & trior nets
(C) Wand & triand nets
(D) Tri0 & tri1 nets
(E) Supply0 & supply1 nets
(F) Trireg nets
DATA TYPES
NET vs PORTS
 Nets are internal signals that cannot be accessed by outside
 Ports are external signals to interface with outside environment

— inputports can be read but cannot be written
— output ports can be written but cannot be read
— inout ports can be read and written
module pc (clk, rst, status, i_o); clk
input clk, rst;
output [3:0] status; addr[9:0]
rst
Processor
inout [7:0] i_o;
Memory
wire r_w; data[7:0]
wire [7:0] data; status[3:0]
wire [9:0] addr; i_o[7:0] r_w
……
endmodule
DATA TYPES
REGISTERS
 A register type represents data storage elements or a variable that can
hold a value
 Do not represent real hardware but real hardware can be implemented

with registers
 It can assign a value only within always or initial statement and default
value of register is X
 Example of how register can be used:

reg CLK; reg A, C; // declaration
initial always
A = 1;
begin
C = A; // C gets the value 1
CLK = 1'b0; A = 0; // C is still 1
#5 CLK = ~CLK; C = 0; // C is now 0
DATA TYPES
REGISTERS TYPES
(a) INTEGER
 A integer register contains integer variable
 It is a general purpose register data type used for manipulating quantities,

typically for high-level behavior
Integer integer1, integer2,……….integer n [msb:lsb]
 Value of MSB and LSB specify the range of an integer array
 Examples:
integer count;
integer addr [3:0];
initial
begin
count=count+1;
DATA TYPES
REGISTERS TYPES
(b) REAL
 Real registers are used to specify the variable in decimal or scientific
notation and they are declared with the keyword real
 Real numbers cannot have a range declaration and their default value is 0,
its syntax is given as
Real real_reg1, real_reg2,……………….real_regn
 Examples:
real pwd;
initial
begin
pwd=3e5;
pwd=2.13;
end

DATA TYPES
REGISTERS TYPES
(c) TIME
 Time register is used to store and manupulate time values
 They are used to store simulation time and it is declared with the keyword
time
 Syntax: Time time_id1, time_id2,………………..time_idn
 Examples:
time currtime;
initial
begin
currtime=$time;
end

DATA TYPES
REGISTERS TYPES
(d) VECTORS
 Net or reg data can be declared as vector, if bit width is not specified, the default
is scalar (1-bit)
 Examples: wire b; //scalar net variable
wire[7:0] databus; //8-bit data bus
Represent buses
wire[3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
Left number is MS bit
Vector assignment (by position!!)
busB[1] = busA[3];
busB[2] = busA[2];
busB[3] = busA[1];
busB[4] = busA[0];
DATA TYPES
REGISTERS TYPES
(e)ARRAY
 Array are used to declare multi-dimensional variable
 Array types are used for reg, integer, data types and array are accessed by:
<array_name>[<subscript>]
 Examples: integer matrix[4:0][0:255]; //two dimensional array of integer

reg[7:0] array1[3:0]; //declare an array of 8-bit vector reg
• Syntax
• Limitation: Cannot access array subfield or
integer count[1:5];//5 integers
entire array at once
reg var[-15:16];//32 1-bit regs
var[2:9] = ???;//WRONG!!
reg [7:0] mem[0:1023];//1024 8-bit regs
• Accessing array elements var = ???;//WRONG!!
– Entire element: mem[10] = 8’b10101010; • Arrays don’t work for the Real data type
– Element subfield (needs temp storage): real r[1:10];//WRONG !!
reg [7:0] temp;
temp = mem[10];
var[6] = temp[2];
DATA TYPES
REGISTERS TYPES
(f) MEMORIES
 A memory is an array of registers it is simply a one-dimensional array of registers
 Each element of array is known as element or word and it is addressed by single array
index
 A memory component can be defined using reg variables

reg [7:0] myMem [3:0]; // It defines a memory with 4 locations and each
// location contains an 8-bit data
Bit 7 6 5 4 3 2 1 0
myMem[0]
myMem[1]
myMem[2]
myMem[3]

DATA TYPES
REGISTERS TYPES
(g) PARAMETERS
 It is a constant and it is used to specify delays and widths of a variables
 Parameter can be assigned a value only once using declaration and its form is
parameter param1=const_expr1, param2=const_expr2,…….paramN=const_exprN;
 Parameter can be changed at compilation time using def param statement
 Example:
……
parameter bussize = 8;
Parameter bit=1, byte=8;
reg [bussize-1 : 0] databus;
……

DATA TYPES
RESTRICTION ON DATA TYPES
• Data Flow and Structural Modeling

– Can use only wire data type
– Cannot use reg data type
• Behavioral Modeling
– Can use only reg data type
(within initial and always constructs)
– Cannot use wire data type

OPERATORS
ARITHMETIC OPERATORS
 +, -, *, /, %,**
 If any operand is x the result is x
 Negative registers:
-regs can be assigned negative but are treated as unsigned
reg [15:0] regA;
..
regA = -4’d12; // stored as 216-12 = 65524
regA/3 evaluates to 21861

OPERATORS
LOGICAL OPERATORS
 &&  logical AND
 ||  logical OR
 !  logical NOT
 Operands evaluated to ONE bit value: 0, 1 or x
 Result is ONE bit value: 0, 1 or x

A = 1; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x

OPERATORS
RELATIONAL OPERATORS
>  greater than
<  less than
>=  greater or equal than
<=  less or equal than
Result is one bit value: 0, 1 or x

1>0 1
’b1x1 <= 0 x
10 < z x
OPERATORS
EQUALITY OPERATORS
 ==  logical equality
Return 0, 1 or x
 !=  logical inequality
 ===  case equality

 !==  case inequality Return 0 or 1

OPERATORS
BITWISE OPERATORS
&  bitwise AND
|  bitwise OR
~  bitwise NOT
^  bitwise XOR
 ~^ or ^~  bitwise XNOR
 Operation on bit by bit basis
c = ~a; c = a ^ b;
c = a & b;

OPERATORS
REDUCTION OPERATORS
&  AND
|  OR
^  XOR
 ~&  NAND
 ~|  NOR
 ~^ or ^~  XNOR
 One multi-bit operand  One single-bit result

a = 4’b1001;
c = |a; // c = 1|0|0|1 = 1
OPERATORS
SHIFT OPERATORS
 >>  shift right
 <<  shift left
 Result is same size as first operand, always zero filled
a = 4’b1010; d = a >> 2; // d = 0010
c = a << 1; // c = 0100
 >>>  arithmetic shift right
 <<<  arithmeticshift left
 Vacant position filled by either LSB (>>>) or MSB (<<<) value
a = 4’b0101; d = a >>>1; // d = 1010
c = a <<<1; // c = 1010
OPERATORS
CONCATENATION OPERATORS
 {op1, op2, ..}  concatenates op1, op2, .. to single number
 Operands must be sized !!

reg a;
reg [2:0] b, c;
..
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!
 Replication ..
catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101
OPERATORS
CONDITIONAL OPERATORS
 cond_expr ? true_expr : false_expr
 Like a 2-to-1 mux ..
A
1
Y
B Y = (sel)? A : B;
0
sel
 For 4-to-1 mux ..

OPERATORS
OPERATORS PRECEDENCE
Use parentheses to
enforce your priority

VERILOG MODELING
STRUCTURAL
DATA FLOW Our focus
BEHAVIORAL
SWITCH

STRUCTURAL MODELING
 At gate level, the circuit is described in terms of gates (e.g., and,

nand)
 Hardware design at this level is intuitive for a user with a basic
knowledge of digital logic design
 Because it is possible to see a one-to-one correspondence
between the logic circuit diagram and the Verilog description
 Actually, the lowest level of abstraction is switch- (transistor-)
level modeling
 However, with designs getting very complex, very few hardware
designers work at switch level. So most of the digital design is
now done at gate level or higher levels of abstraction.
STRUCTURAL MODELING
GATE PRIMITIVES
 All logic circuits can be designed by using basic gates. Verilog
supports basic logic gates as predefined primitives. There are
three classes of basic gates.
 Multiple-input gates: and, or, nand, nor, xor, xnor

 Multiple-output gates: buffer, not
 Tristate gates: bufif0, bufif1, notif0, notif1
 These primitives are instantiated like modules except that they

are predefined in Verilog and do not need a module definition.
 Logic gates can be used in design using gate instantiation. A simple

format of a gate instantiation is,
Gate_type [instance_name] (term1, term2,……………..termn);
STRUCTURAL MODELING
Basic syntax for multiple-input gates is:
Multiple_input_Gate_type [instance_name] (output, input1, input2,……..inputn);
AND GATE
// Module Name: Andgate
module Andgate(i1, i2, out);
input i1;
input i2;
output out;
and (out,i1,i2);
endmodule
OR GATE
// Module Name: Orgate
module Orgate(i1, i2, out);
input i1;
input i2;
output out;
or(out,i1,i2);
endmodule
STRUCTURAL MODELING
NAND GATE
// Module Name: Nandgate
module Nandgate(i1, i2, out);
input i1;
input i2;
output out;
nand(out,i1,i2);
endmodule
NOR GATE
// Module Name: Norgate
module Norgate(i1, i2, out);
input i1;
input i2;
output out;
nor(out,i1,i2);
endmodule
STRUCTURAL MODELING
XOR GATE
// Module Name: Xorgate

module Xorgate(i1, i2, out);
input i1;
input i2;
output out;
xor(out,i1,i2);
endmodule
XNOR GATE
// Module Name: Xnorgate
module Xnorgate(i1, i2, out);
input i1;
input i2;
output out;
xnor(out,i1,i2);
endmodule
STRUCTURAL MODELING
Basic syntax for multiple-output gates is:
Multiple_output_Gate_type [instance_name] (output1, output2,……..outputn, input);
BUFFER GATE
// Module Name: Buffer
module Buffer(in, out);
input in;
output out;
buf(out,in);
endmodule
NOT GATE
// Module Name: Notgate
module Notgate(in, out);
input in;
output out;
not(out,in);
endmodule
STRUCTURAL MODELING
Basic syntax for tristate-gates is:
Tristate_type [instance_name] (output,input,control);
BUFIF1 GATE
// Module Name: Bufif1
in out module Bufif1(in, out, con);
input in,con;
Out=in if con=1
output out;
con Else out=Z
bufif1(out,in,con);
endmodule
BUFIF0 GATE
// Module Name: Bufif0
module Bufif0(in, out, con);
in out input in,con;
Out=in if con=0 output out;
con Else out=Z bufif0(out,in,con);
endmodule
STRUCTURAL MODELING
NOTIF1 GATE
// Module Name: notif1

module notif1(in, out, con);
in out
input in,con;
Out=in if con=1 output out;
con Else out=Z notif1(out,in,con);
endmodule
NOTIF0 GATE
// Module Name: notif0

in out module notif0(in, out, con);
input in,con;
Out=in if con=0
Else out=Z output out;
con
notif0(out,in,con);
endmodule

STRUCTURAL MODELING
EXAMPLE – 2:1 MUX

STRUCTURAL MODELING
MODULE

STRUCTURAL MODELING
MODULE NAME

STRUCTURAL MODELING
PORT LIST

STRUCTURAL MODELING
INPUT/OUTPUT DECLARATION

STRUCTURAL MODELING
DATA TYPE DECLARATION

STRUCTURAL MODELING
GATE INSTATIATION

STRUCTURAL MODELING
GATE INSTATIATION

STRUCTURAL MODELING
HALF ADDER
// Module Name: HalfAdder

module HalfAdder(sum, c_out, i1, i2);
output sum;
output c_out;
input i1;
input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule

STRUCTURAL MODELING
FULL ADDER USING MODULE INSTATIATION
// Module Name: FullAdder

module FullAdder(sum, c_out, i1, i2,c_in);
output sum;
output c_out;
input i1;
input i2;
input c_in;
wire s1,c1,c2;
HalfAdder HA1(s1, c1, i1, i2);
HalfAdder HA2(sum, c2 ,s1,c_in);
or(c_out,c1,c2);
endmodule

STRUCTURAL MODELING
4-BIT PARALLEL ADDER USING MODULE INSTATIATION
module adder_4bit (S, COUT,A,B);
output [3:0]S ;
output COUT ;
input [3:0] A ;
input [3:0] B ;
wire [2:0]C;
FullAdder FA0(S[0],C[0],A[0],B[0],1'b0);
FullAdder FA1(S[1],C[1],A[1],B[1],C[0]);
FullAdder FA2(S[2],C[2],A[2],B[2],C[1]);
FullAdder FA3(S[3],COUT,A[3],B[3],C[2]);
endmodule
STRUCTURAL MODELING
// Module Name: Mux4to1
4:1 MUX module Mux4to1(i0, i1, i2, i3, s0, s1, out);
input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output out;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule
STRUCTURAL MODELING
// Module Name: Dux1to4
1:4 DEMUX
module Dux1to4(in, s0, s1, out0, out1, out2, out3);
input in;
input s0;
input s1;
output out0;
output out1;
output out2;
output out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule

STRUCTURAL MODELING
2:4 DECODER
FULL ADDER

STRUCTURAL MODELING
EXERCISE
 Binary Subtractor
 Parallel Adder
 Binary Multiplier
 Magnitude Comparator-4 bit
 Decoders
 Encoders
 Mux
 Demux
 Parity generator and checker.

BEHAVIORAL MODELING

BEHAVIORAL MODELING
 Behavioral model enables you to describe the system at a higher
level of abstraction
 All we need to do is to describe the behavior of our design

 Action  How the model of our circuit should behave?
 Timing control  At what time do what thing & At what condition do
what thing
 Verilog supports the following construct to model circuit

behavior
 Procedural block
 Procedural assignment
 Timing controls
 Block statement
 Conditional statement

BEHAVIORAL MODELING
PROCEDURAL BLOCK
 In Verilog procedural block are the basic of behavior modeling
 We can describe a one logic in one procedural block
 Procedural block types: (i) initial (ii) always
 All initial & always statement execute concurrently starting at time t=0
 A module may contain any number of initial & always statement
 Structure of procedural block
Type of block: initial or always
type-of-block @ (sensitivity list)
Symbol used to signifies event
begin : name-of-block; (only for always block)
local variable declaration;
Specify the event which starts the execution of the
procedural assignment statements;block (only for always block)
end
A block can assign a name for the block
Variables which are local to the block are
defined here
This form the body of the block
All action within blocks are enclosed by begin-
end construct
BEHAVIORAL MODELING
PROCEDURAL BLOCK - INITIAL STATEMENT
 Initial statement causes procedural statement to executes only once and it begin
its execution at start of simulation time 0.
 Sequential block (begin-end) is the most commonly used procedural statement,

that is it wait for a certain time until an event occurs
Syntax: initial [timing_controls] procedural statements
Example: initial #2 a=0
Example: //initial statement with sequential block

reg a,b;
initial
begin
a=1`b0;
b=1`b1;
#5 a=1`b1;
end;
BEHAVIORAL MODELING
PROCEDURAL BLOCK - ALWAYS STATEMENT
 For circuit synthesis we use the always block and such a block
must contain all sequential constructs
 Note that the statements in an always block between begin/end

are executed sequentially just as they are written
 Variables assigned a value inside an always block must be of type

reg or integer
 The if, case, for loop, and while loop must appear inside an always
block
 A module can have multiple blocks, but blocks cannot be nested
 For modules that have multiple always blocks all of the always
blocks are executed in parallel
BEHAVIORAL MODELING
PROCEDURAL BLOCK - ALWAYS STATEMENT
 Always blocks are repeated executed until simulation is stopped. Similar to
initial block it begin its execution at start of simulation time 0.
 This statement is used to model a block of activity that is repeated continuously

in a digital circuit. Example:
module clock_gen;
reg clock, temp;
//Initialize clock at time zero

Initial clock = 1‘b0;
Syntax: always [timing_control] procedural statement
(or) //Toggle clock every half-cycle
always @(sensitivity_list) always #10 clock = -clock;
begin
/*sequential statements always @ (posedge clock)
consisting of assignment, begin
if, case, while, and for loops */ temp=temp+1;
end end
BEHAVIORAL MODELING
PROCEDURAL STATEMENT
 The assignment statement within an initial statement or always
statement is called procedural statement
 It is used to assign to only a register data type
 Procedural statement executes sequentially respect to other
statements that appear around it
 Sequential block always start execution when an event occurs.
 Two types of procedural assignments are: (i) blocking assignment
Example: always @ (clk)
(ii) non-blocking assignment
begin
reg count=z;
count=count+1;
z=count;
end

BEHAVIORAL MODELING
BLOCKING PROCEDURAL ASSIGNMENT
 A procedural statement in which the assignment operator is an “=“ in a blocking
procedural assignment Example: reg B=55;
 Blocking procedural assignment is executed before any of the statement that follow it are
executed
Example: // Full adder using blocking procedural statement
module FA(sum,cout,A,B,C)
input A,B,C;
output sum, cout;
always @ ( A or B or C)
begin
reg C1,C2,C3;
sum=A&C;
C1=A&B;
C2=B&C;
C3=A&C;
Cout= C1|C2|C3;
end
endmodule
 The sum assignment occurs first, sum is computed, then second statement is executes C1
is assigned and then third executed and C2 is assigned and so on
BEHAVIORAL MODELING
NON-BLOCKING PROCEDURAL ASSIGNMENT
 The main characteristics of non-blocking assignment statement is
execution is performed concurrently
Example: c<=a&b;
 In non-blocking assignment the assignment symbol “<=“ is used
Example:
always @ ( posedge clk)
begin
a<=b;
@ (negedge clk)
c<=b&(~c);
#2 b<=c;
endmodule
 ‘a’ is assigned the stored value of ‘b’ this activity is carried out concurrently
 At the negative edge clock ‘c’ is assigned a value of b&(~c)
 Two nanoseconds later positive edge clock assign ‘c’ value to ‘b’

BEHAVIORAL MODELING
BLOCKING vs NONBLOCKING
Blocking Non-blocking
 <variable> = <statement>  <variable> <= <statement>
 Similar to C code  The inputs are stored once the

procedure is triggered
 The next assignment waits
until the present one is  Statements are executed in
finished parallel
 Used for combinational logic  Used for flip-flops, latches and

registers
Do not mix both assignments in one
procedure
BEHAVIORAL MODELING
BLOCKING STATEMENT - SEQUENTIAL BLOCK
 Block statements are used to group multiple statements to act together as one. There are
two types of blocks: sequential blocks and parallel blocks
 The keywords begin and end are used to group statements into sequential blocks.
 Sequential blocks have the following characteristics:
 The statements in a sequential block are processed in the order they are specified
 A statement is executed only after its preceding statement completes execution
 If delay or event control is specified, it is relative to the simulation time when the previous statement in the
block completed execution
//Illustration 1: Sequential block without delay //Illustration 2: Sequential blocks with delay
reg X, Y; reg x, y;
reg [1:0] z, w; reg [1:0] z , w;
initial initial
Begin begin
x = l'bO; x = l'bo; //completes at simulation time 0
y = l‘b1; #5 y = l'bl; //completes at simulation time 5
z = {x, y}; #10 z = {x, y}; //completes at simulation time 15
w = {y, x}; #20 w = {y, x); //completes at simulation time 35
End end

BEHAVIORAL MODELING
BLOCKING STATEMENT - PARALLEL BLOCK
 Parallel blocks, specified by keywords fork and join, provide interesting
simulation features
 Parallel blocks have the following characteristics:

– Statements in a parallel block are executed concurrently
– Ordering of statements is controlled by the delay or event control assigned to each statement
– If delay or event control is specified, it is relative to the time the block was entered
 All statements in a parallel block start at the time when the block was entered.
Thus, the order in which the statements are written in the block is not
important. //Example : Parallel blocks with delay
reg x, y;
reg [ 1 : 0 ] z, w;
 The result of simulation remains the same initial
fork
except that all statements start in parallel x = l'bO; //completes at simulation time 0
#5 y = l'b1; //completes at simulation time 5
at time 0. Hence, the block finishes at #10 z {x, y}; //completes at simulation time 10
time 20 instead of time 35. #20 w = {y, x}; //completes at simulation time
join

BEHAVIORAL MODELING
CONDITIONAL STATEMENT - IF
 Conditional statements are used for making decisions based upon certain
conditions
 These conditions are used to decide whether or not a statement should execute
 If the condition evaluates to a non zero known value, then procedural_statement1

is executed Example:
module
mux(out,a,b,sel);
 If condition_ 1 evaluates 0.x,z, then procedural_statement2 input a,b,sel;
output out;
is not executed and an else branch, if it exist, is executed reg out;
always @ (a,b)
Syntax:
begin
if (condition_1) if (sel==1’b0)
procedural staement_1 out=a;
else if (condition_2) else
procedural staement_2 out=b;
else (condition_3) end
procedural staement_3 endmodule

BEHAVIORAL MODELING
CONDITIONAL STATEMENT - CASE
 The keywords case, endcase, and default are used in the case statement
 The expression is compared to the alternatives in the order they are written
 For the first alternative that matches, the corresponding statement or block is
executed. If none of the alternatives match, the default_statement is executed.
The default_statement is optional. module mux4_to_1 (out, iO, i1, i2, i3, sl, sO);
input iO, i1, i2, i3;
input s1. sO; //Port declarations from the I/O diagram
output out;
syntax:
reg out;
always @(sl or sO or iO or i1 or i2 or i3)
case(case_expression)
case ({sl, sO}) //Switch based on concatenation signals
case_item_expression {case_item_expression}
2'dO out iO;
procedural statement
2'd1 out i1;
………
2'd2 out i2;
………
2'd3 out i3;
default:procedural_statement
default: $display("Invalid control signals");
endcase
endcase
endmodule
UNIT-III : LECTURE30 ECE2003 – DIGITAL LOGIC DESIGN 90

BEHAVIORAL MODELING
CONDITIONAL STATEMENT - CASE
Case treats each value 0, 1, x, and z literally
 4ʼb01xz only matches 4ʼb01xz
 Example: 4ʼb0110 does not match 4ʼb01xx in a case
Casez treats 0, 1, and x literally

 Casez treats z as a donʼt care
 Example: 4ʼb0110 matches 4ʼb01zz, but not 4ʼb01xz
Casex treats 0 and 1 literally

 Casex treats both x and z as donʼt cares
 Example: 4ʼb0110 matches 4ʼb01xx and also 4ʼb01xz

BEHAVIORAL MODELING
CONDITIONAL STATEMENT - FORLOOP
 When a circuit exhibits regularity, a for loop can be used inside an

always statement to simplify the design description (for loop is a
procedural statement used only inside an always block)
 C style syntax: for (k = 0; k < 4; k = k+1)

 Loop index must be type integer (not reg!)
 Can`t use the convenience of k++
 Use begin …end for multiple statements in the loop
 Each iteration of the loop specifies a different piece of the circuit

 Has nothing to do with changes over “time”

BEHAVIORAL MODELING
CONDITIONAL STATEMENT - WHILE LOOP
 All looping statements can appear only inside an initial or always block. Loops
may contain delay expressions
 The while loop executes until the while-expression becomes false. If the loop is
entered when the while-expression is false, the loop is not executed at all
 If multiple statements are to be executed in the loop, they must be grouped

typically using keywords begin and end.
//Increment count from 0 to 127. Exit at count 128.
integer count;
syntax: initial
begin
While(condition) count = 0;
Procedural_statements while (count < 128)
begin
$display("Count = %d", count); //Display the count
count = count + 1;
end
BEHAVIORAL MODELING
CONDITIONAL STATEMENT - REPEAT LOOP
 The keyword repeat is used for this loop. The repeat construct executes the loop a fixed
number of times.
 A repeat construct cannot be used to loop on a general logical expression. A while loop is
used for that purpose.
 A repeat construct must contain a number, which can be a constant, or a variable value.
 However, if the number is a variable or signal value, it is evaluated only when the loop
starts and not during the loop execution. //EXAMPLE : increment and display count from a to 127
integer count;
initial
begin
syntax:
count = 0;
repeat(128)
repeat [loop count] begin
procedural_statement $display("Count = %d", count);
count = count + 1;
end
end

BEHAVIORAL MODELING
CONDITIONAL STATEMENT - FOREVER LOOP
 The keyword forever is used to express this loop. A forever loop can be exited by
use of the disable statement.
 The loop does not contain any expression and executes forever until the $finish
task is encountered.
 The loop is equivalent to a while loop with an expression that always true, e.g.,
while (1).
 A forever loop is typically used in conjunction with timing control constructs.

//Example : Clock generation
//Use forever loop instead of always block
syntax: reg clock;
initial
forever begin
procedural_statement clock = 1'b0;
forever #10 clock=-clock; //Clock with period of 20 units
end
BEHAVIORAL MODELING
FULL ADDER

BEHAVIORAL MODELING
4x1 MUX

BEHAVIORAL MODELING
2 to 4 DECODER

BEHAVIORAL MODELING
2 to 4 DECODER

BEHAVIORAL MODELING
4 to 2 ENCODER

BEHAVIORAL MODELING
4 to 2 PRIORITY ENCODER

BEHAVIORAL MODELING
4 to 2 PRIORITY ENCODER

DATAFLOW MODELING
 Data flow level description of a digital circuit is at higher level, it makes the
circuit description more compact as compared to design through gate
primitives
 Design implement using data flow modeling uses a continuous assignment

statement and Verilog provides different operators to perform a function
 The assignment statement start with the keyword assign and results are
assigned to nets
 Continuous assignment – most basic statement used to drive value onto net
Syntax: assign LHS_target=RHS_expression
Example: wire c,a,b; //net declaration

assign c=a&b; //continuous assignment

DATAFLOW MODELING
 Implicit continuous assignment – it is the shortcut method of assigning the
expression on the net
Example: //regular continuous assignment
wire c,a,b;
assign c=a&b;
//implicit continuous assignment
wire c=a&b;
 Implicit net declaration – if a signal name of the left hand side of the continuous
assignment statement is not declared the verilog simulator assign an implicit net
declaration for the net
Example: //continuous assignment

wire a,b;
assign c=a&b; // here c is not declared as a wire
/* but simulator automatically delare it as wire
if we use implicit net delaration statement */

DATAFLOW MODELING
 Regular assignment delay – the assignment takes effect with the time delay of 2 time
steps. If the values of ‘a’ and ‘b’ changes then ‘c’ wait for two time steps to compute
the result.
Example: wire c,a,b;

assign #2 c=a&b;
 Implicit continuous assignment delay – it is a shortcut method of assigning the delay

and the expression on the net
Example: wire #5 c=a&b;
 Net declaration delay – a delay can be specified on a net when it is declared without
putting a continuous assignment on the net
Example: wire #5 c;
assign c=a&b;

DATAFLOW MODELING
EXPRESSIONS
 An expression is formed using operands & operators
 Expression can be used whenever a value is expected
 Example: a & b, x1[7:0] + x2[7:0]
OPERANDS
 Operands are the data types used in the expression
 An operands can be constant, net, parameter, register, memory, bit select
 Example: c = a + b // a, b, c are real operands
OPERATORS
 Operators act on operands to produce desired result
 Various types: arithmetic, logical, relational, equality, bitwise, shift, etc.,
 Example: c = a % b // % is operator to perform modules operation on a,b
DATAFLOW MODELING
HALF ADDER FULL ADDER
module halfadder(s,c,a,b); module fa_da(a,b,cin,sum,cout);

input a,b; input a,b,cin;
output s,c; output sum,cout;
assign s=a^b; assign sum=a^b^cin;
assign c=a&b; assign cout=(a&cin)|(b&cin)|(a&b);
endmodule endmodule

DATAFLOW MODELING
8:1 MUX
module mux(y,s,i);
input [2:0]s;
input[7:0]i;
output y;
assign y= (~s[2] & ~s[1] & ~s[0] & i[1]) | (~s[2] &
~s[1] & s[0] & i[2]) | (~s[2] & s[1] & ~s[0] &
i[3]) | (~s[2] & s[1] & s[0] & i[4]) | (s[2] & ~s[1] &
~s[0] & i[5]) | (~s[2] & s[1] & ~s[0] & i[6]) | (s[2] &
s[1] & ~s[0] & i[7]) | (s[2] & s[1] & s[0] & i[8]);
endmodule

DATAFLOW MODELING
BINARY TO GRAY CODE CONVERTER
module binary_to_gray(g,b);
input [3:0]b;
output[3:0]g;
assign g[3]= b[3];
assign g[2]= b[2]^b[3];
assign g[1]= b[1]^b[2];
assign g[0]= b[0]^b[1];
endmodule

DATAFLOW MODELING
9-BIT PARITY GENERATOR
module parity(even,odd,d);
input [8:0]d;
output even, odd;
wire e0,e1,e2,e3,f0,f1,h0; d[0] e0
assign e0=d[0]^d[1]; d[1] f0
assign e1=d[2]^d[3]; d[2]
assign e2=d[4]^d[5]; d[3] e1 h0
even
assign e3=d[6]^d[7]; d[4] e2 odd
assign f0=e0ê1; d[5]
assign f1=e2ê3; d[6] f1
assign h0=f0^f1; d[7] e3
assign odd=h0^d[8]; d[8]
assign even=~odd;
endmodule

DATAFLOW MODELING
8:3 PRIORITY ENCODER
module PriorityEncoder_DataFlow(code,data);
input[7:0]data;
output[2:0]code;
wire [7:0]w;
assign w[0]=(~data[0]);
assign code[0]=(w[7]&w[6]&w[5]&w[4]&w[3]&w[2]&data[1])|
(w[7]&w[6]&w[5]&w[4]&data[3])|(w[7]&w[6]&data[5])|data[7];
assign code[1]=(w[7]&w[6]&w[5]&w[4]&w[3]&data[2])|
(w[7]&w[6]&w[5]&w[4]&data[3])|(w[7]&data[6])|data[7];
assign code[2]=(w[7]&w[6]&w[5]&data[4])|(w[7]&w[6]&data[5])|(w[7]&data[6])|data[7];
endmodule
TEST BENCH
INTRODUCTION
 We need to apply appropriate stimulus to the design in order to
test it. This can be done by writing another Verilog code called the
‘Test Bench’. This is written as a separate file, different from the
design file(s).
 Stimulus is nothing but the application of various permutations and

combinations of inputs at various points of time and, looking for
correct results produced by the design.
 The design may comprise of just one module or several modules
depending upon the complexity of the application. As mentioned
earlier, the test bench applies appropriate test pattern to the inputs
of the design under test and checks the outputs of the design so as
to verify its functionality.
TEST BENCH
STRUCTURE
module test_module_name;
//declare local reg and wire identifiers.
//instantiate the design module under test
//generate stimulus (inputs to design module) using initial and always.
// display output response.(display on screen or print)
endmodule
Examples:
$display("%d %b %b",A,B,C);
$monitor($time„"%b %b %h" , s1,s2,outvalue);

TEST BENCH
INTRODUCTION

TEST BENCH
INTRODUCTION

TEST BENCH

TEST BENCH – AND GATE

TEST BENCH – HALF ADDER

TEST BENCH – FULL ADDER

TEST BENCH – FULL ADDER

TEST BENCH – 4:1 MUX

TEST BENCH – 4:1 MUX

TEST BENCH – D-FLIP FLOP
TEST BENCH:
module dflipflopt_b;
reg d;
D FLIPFLOP reg clk;
module dflipflopmod(q, d, clk);
wire q;
output q;
input d;
dflipflopmod uut (.q(q),.d(d), .clk(clk) );
input clk; initial begin
reg q; // Initialize Inputs
always @(posedge clk) d = 0;
q=d; clk = 0;
endmodule end
always #3 clk=~clk;
always #5 d=~d;
endmodule

DEBUGGING AND ERROR CHECKING
 The following Verilog code is supposed to describe a circuit that has an 8-

bit data input, an 8-bit data output, plus two additional single-bit outputs.
The over_flow output is strictly combinatorial. You may assume that the
operations to produce data_out, carry_out and over_flow are correct (i.e.
the functional specification for these values is correct). However, syntax
errors for these statements do exist.
 Examine the code below and identify any errors that would prevent this
code from compiling and synthesizing properly. These errors may include
syntax errors, logical design errors or needed lines that are missing from
the code. Indicate the modifications you would make to the code to make
it work. Include comments beside these modifications or the portion of
the code that is incorrect. There are 20 errors in the code below.

module bad_module is (clk,
reset,
[7:0] data_in,
data_out;
carry out,
over_flow )
input clk;
input reset;
input carry_in;
input data_in;
output data_out;
output carry_out;
output over_flow;
reg [7:0] data_out;
reg carry_out, overflow;

always @ (posedge clk | posedge reset) ;

if reset
then
data_out = 0;
carry_out = 0;
Else
data_out = (data_in * 2) + carry_in;

carry out = ~& data_in[7,6];
over_flow = data_out(7);
end module

module bad_module (clk, (1) Removed “is” after module
reset,
data_in, (2) Removed [7:0]
carry_in, (3) Added carry_in
data_out, (4) Changed “;” to “,”
carry_out, (5) Changed “carry out” to “carry_out”
over_flow ) (6) Semicolon at the end of module definition
input clk;
input reset;
input carry_in;
input [7:0] data_in; (7) Added [7:0]
output [7:0] data_out; (8) Added [7:0]
output carry_out;
output over_flow;
reg [7:0] data_out;
reg carry_out;
always @ (posedge clk or posedge reset) (9) Changed “|” to “or”
(10)No semicolon for always statement
if (reset) (11) Added Parentheses around “reset”
(12) Removed “then”
begin (13) Added “begin”
data_out = 0;
carry_out = 0;
end (14) Added “end”
else (15) “else” keyword must be lower case
begin (16) Added “begin”
data_out = (data_in * 2) + carry_in;
carry_out = ~& data_in[7:6]; (17) Replace “,” with “:”
end (18) Added “end”
assign over_flow = data_out[7]; (19) Changed “out7” to “out[7]”
endmodule (20) Removed space between “end” & “module”

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MODULE-5

• Ports and Modules

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 2

 The fundamental characteristics of a digital system are

 HDL is a language used to describe digital system.

 The goal of an HDL is to describe and model digital

 Different HDLs are available different purpose such as

 There are other, limited capability, languages such as

 It is most commonly used in the design and verification

 It is also used in the verification of analog

 One of the two most common HDL used by IC designers

 Verilog Modeling ranges from Gate to Processor level and

 In-build primitive logic gates (AND, OR, NAND etc) and

 Verilog versions: Verilog-95, 2001, 2005, System Verilog

 Verilog is case-sensitive and its file extension is .v

Quartus-II VeriWell Tarang EDA

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 8

VERILOG HDL VHDL

VERIfiable LOGarithmic HDL Very high speed integrated circuit HDL

Developed based on C-language Developed based on ADA-language

Easy to learn and understand Difficult to learn and understand

Case sensitive No case sensitive

It allows switch-level modelling switch-level modelling is not possible

Very simple data types Complex data types

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 9

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 10

// A simple example comment line

module and2 (a, b ,c); module name  Circuit

assign c = a & b; body

endmodule end module

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 11

• General definition  Example

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 14

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 15

module MAT (enable, data, all_zero, result, status);

 To make code easy to read, use self-explanatory port names

 For the purpose of conciseness, use short port names

 In vector port declaration, MSB can be smaller index.

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 16

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 18

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 19

 Some of examples are

 An escaped keyword is not treated as same as the keyword

 The identifier \ begin is distinct from the identifier begin

/* Multiple line comment*/

/* Nesting /* comments */ do NOT work */

represents low logic level or false condition

represents high logic level or true condition

represents unknown logic level

represents high impedance logic level

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 23

• Underscore character and question marks

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 26

– Extending the most-significant part

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 28

 Syntax for net declaration:

 Net is a value determined from the value of its drivers

(A) Wire & tri-nets

 Ports are external signals to interface with outside environment

/* Nesting /* comments / do NOT work /