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Solution of Verilog HDL by Samir Palnitkar

The document defines functions and tasks for numerical calculations. It defines a function to calculate the factorial of a 4-bit number with a 32-bit output. Another function multiplies two 4-bit numbers with an 8-bit output. A task computes the factorial of a 4-bit number with a 32-bit output and 10 time unit delay. Another task computes the parity of a 16-bit number with a 1-bit output delayed 3 clock cycles using a repeat loop. It also mentions designing a traffic signal controller using events, tasks and functions.

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MANISH KUMAR
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10K views

Solution of Verilog HDL by Samir Palnitkar

The document defines functions and tasks for numerical calculations. It defines a function to calculate the factorial of a 4-bit number with a 32-bit output. Another function multiplies two 4-bit numbers with an 8-bit output. A task computes the factorial of a 4-bit number with a 32-bit output and 10 time unit delay. Another task computes the parity of a 16-bit number with a 1-bit output delayed 3 clock cycles using a repeat loop. It also mentions designing a traffic signal controller using events, tasks and functions.

Uploaded by

MANISH KUMAR
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Sol Task and functions CH-8

Define a function to calculate the factorial of a 4-bit number. The output is a 32-bit value.

2. Define a function to multiply two 4-bit numbers a and b. The output is an 8-bit value. Invoke the function by using stimulus and check results.

Define a task to compute the factorial of a 4-bit number. The output is a 32bit value. The result is assigned to the output after a delay of 10 time units.

Define a task to compute even parity of a 16-bit number. The result is a 1-bit value that is assigned to the output after three positive edges of clock.(Hint: Use a repeat loop in the task).

6.Using named events, tasks, and functions, design the traffic signal controller in Traffic Signal Controller

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