C S 8201 Digital Principles and System Design PDF

R o l l Number:
B. E . / B . T e c h . ( F T ) D E G R E E E N D S E M E S T E R E X A M I N A T I O N S , A P R I L / M A Y 2014
COMPUTER SCIENCE AND ENGINEERING
II S E M E S T E R
C S 8201 D I G I T A L P R I N C I P L E S A N D S Y S T E M D E S I G N
(Regulation 2 0 1 2 )
Time: Three Hours A n s w e r AH Q u e s t i o n s Max. M a r k s : 100
P A R T - A (10 X 2 = 20 M a r k s )
1. C o n v e r t the hex n u m b e r F 3 A 2 to binary a n d octal.
2. S h o w that that t h e e x c e s s -3 c o d e is self c o m p l e m e n t i n g .
3. Is the N A N D f u n c t i o n associative? Justify.
4. T h e main stairway in a block of flats has three switches for controlling the lights.
S w i t c h A is located at the top of the stairs, switch B is located h a l f w a y up the stairs a n d
switch C is positioned at the bottom of the stairs. D e s i g n a c o m b i n a t i o n a l circuit to
control the lights o n t h e staircase.
5. G i v e the H D L d e s c r i p t i o n of a positive e d g e triggered J K flip flop.
6. S h o w h o w t i m i n g signals can be g e n e r a t e d using a binary c o u n t e r a n d a d e c o d e r .
7. W h a t is an e s s e n t i a l h a z a r d ?
8. C o m m e n t o n t h e circuit w h o s e transition t a b l e is s h o w n b e l o w :
XiX 2
00 01 11 10
00 00 11 01 00
01 00 01 00 01
11 01 11 10 11
10 10 11 01 10
9. W h a t is a n F P G A ?
10. Differentiate b e t w e e n a P L A a n d a P A L .
P A R T - B ( 5 x 1 6 = 80 Marks)
1 1 . (i) Simplify F ( A , B , C , D ) = 1(1,2,3,5,6,7,10,11), d ( A , B , C , D ) = £ ( 9 , 1 2 , 1 5 ) using K a r n a u g h

m a p . D r a w t h e logic d i a g r a m using N A N D gates only. (8)
(ii) Simplify t h e B o o l e a n expression F (A, B, C, D) = B + B C D + B ' C D + A B + A ' B + B ' C .
Indicate the t h e o r e m s u s e d . (4)
(iii) E x p r e s s t h e following function as a s u m of m i n t e r m s a n d as a product of

m a x t e r m s : F (A.B.C.D) = B ' D + A ' D + B D . (4)
12. a) (i) D i s c u s s t h e principle of o p e r a t i o n of carry-look a h e a d a d d e r s . (10)

D e s i g n a 4-bit carry-look a h e a d adder a n d draw t h e circuit. C a l c u l a t e t h e delay
for g e n e r a t i n g s a n d c .
3 4
(ii) D e s i g n a 3x3 binary multiplier circuit. (6)
(OR)
b) (i) D e s i g n a four-input priority e n c o d e r with the D input having the highest priority
0
a n d t h e D input having the least priority.

3 (10)
(ii) W r i t e a V e r i l o g H D L m o d e l for t h e priority e n c o d e r g i v e n a b o v e . (6)
13. a) (i) D e s i g n a c o u n t e r with the following r e p e a t e d binary s e q u e n c e :

0, 1 , 3, 5, 7, 0 U s e J-K flip flops. (10)
(ii) D r a w t h e circuit of a four-bit universal shift register a n d d i s c u s s its o p e r a t i o n . (6)
(OR)
b ) (i) D i s c u s s t h e d e s i g n of a 4-bit u p / d o w n binary ripple c o u n t e r using T flip flops. (10)
(ii) R e d u c e t h e n u m b e r of states in t h e following state table a n d tabulate the state

table:
Present Next state Output
state x=0 x=1 x=0 x=1
a f b 0 0
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0
Starting f r o m state a a n d the input s e q u e n c e 0-1100010001, d e t e r m i n e the

output s e q u e n c e for t h e original state table a n d the r e d u c e d state table. C o m p a r e
t h e results. (6)
14. a) For t h e t w o - i n p u t , t w o - o u t p u t s y s t e m , w h o s e primitive f l o w table is s h o w n below,

perform t h e f o l l o w i n g : (4+2+2+2+6)
• M e r g e t h e f l o w table by f i n d i n g all compatible pairs using a n implication table
• Find the maximal compatibles through a merger diagram
• Find t h e m i n i m a l set of c o m p a t i b l e s that cover-s all t h e s t a t e s a n d is c l o s e d
Do a race-free state a s s i g n m e n t
D e s i g n t h e circuit
xix 2
00 01 11 10
1 1/00 2/00 -/-- 7/00
2 1/00 2/00 5/-0 -/--
3 1/-0 3/10 5/10 -/--
4 1/0- 4/01 6/01 -/--
5 -/-- 3/10 5/10 8/10
6 -/-- 4/01 6/01 9/01
7 1/00 -/-- 6/0- 7/00
8 1/-0 -/-- 5/10 8/10
9 1/0- -/-- 6/01 9/01
(OR)
b) (i) A n a s y n c h r o n o u s sequential circuit is described by t h e excitation function

Y = xix ' + (x, + x ' )y
2 2
a n d t h e output function z = y.
D r a w t h e logic d i a g r a m of t h e circuit. (2)

Derive t h e transition table a n d o u t p u t m a p . (4)
O b t a i n a f l o w table for the circuit. (2)
Describe t h e behavior of t h e circuit. (2)
(ii) W h a t is a static h a z a r d ? Discuss with e x a m p l e s .

Find a circuit that h a s no static h a z a r d s a n d i m p l e m e n t s t h e B o o l e a n function
F ( A , B , C , D ) = 1(3,4,5,6,11,12,13,14,15) (6)
15. a) (i) Give t h e logic d i a g r a m of a basic R A M cell a n d d i s c u s s .

S h o w h o w a 6 4 K X 8 R A M c a n be constructed, indicating all t h e c o n n e c t i o n s a n d
the d e c o d i n g logic required. U s e t w o - d i m e n s i o n a l d e c o d i n g . (10)
(ii) A 12-bit H a m m i n g code w o r d containing 8 bits of d a t a a n d 4 parity bits is r e a d

f r o m m e m o r y . W h a t w a s t h e original 8-bit data w o r d that w a s written into
m e m o r y , if t h e 12-bit w o r d r e a d out is a s follows: (6)
1. 0 0 0 0 1 1 1 0 1 0 1 0
2. 1 0 1 1 1 0 0 0 0 1 1 0
(OR)
b) (i) Discuss t h e construction of a typical R O M . (10)

W h a t a r e t h e different types of R O M ?
S h o w h o w a R O M c a n be u s e d t o i m p l e m e n t a c o m b i n a t i o n a l circuit that
finds t h e nine's c o m p l e m e n t of a B C D digit.
(ii) S h o w h o w t h e following functions c a n b e i m p l e m e n t e d using a PLA: (6)

F1 ( A . B . C . D ) = 1 2 , 3 , 6 , 7 , 1 1 , 1 5 a n d F 2 (A.B.C.D) = 1 0 , 2 , 4 , 6 , 8 , 9 , 1 1 , 1 2 , 1 3 , 1 5
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R o l l Number:

COMPUTER SCIENCE AND ENGINEERING

Time: Three Hours A n s w e r AH Q u e s t i o n s Max. M a r k s : 100

1. C o n v e r t the hex n u m b e r F 3 A 2 to binary a n d octal.

2. S h o w that that t h e e x c e s s -3 c o d e is self c o m p l e m e n t i n g .

3. Is the N A N D f u n c t i o n associative? Justify.

5. G i v e the H D L d e s c r i p t i o n of a positive e d g e triggered J K flip flop.

6. S h o w h o w t i m i n g signals can be g e n e r a t e d using a binary c o u n t e r a n d a d e c o d e r .

1 1 . (i) Simplify F ( A , B , C , D ) = 1(1,2,3,5,6,7,10,11), d ( A , B , C , D ) = £ ( 9 , 1 2 , 1 5 ) using K a r n a u g h

(iii) E x p r e s s t h e following function as a s u m of m i n t e r m s a n d as a product of

12. a) (i) D i s c u s s t h e principle of o p e r a t i o n of carry-look a h e a d a d d e r s . (10)

(ii) D e s i g n a 3x3 binary multiplier circuit. (6)

a n d t h e D input having the least priority.

(ii) W r i t e a V e r i l o g H D L m o d e l for t h e priority e n c o d e r g i v e n a b o v e . (6)

13. a) (i) D e s i g n a c o u n t e r with the following r e p e a t e d binary s e q u e n c e :

(ii) D r a w t h e circuit of a four-bit universal shift register a n d d i s c u s s its o p e r a t i o n . (6)

b ) (i) D i s c u s s t h e d e s i g n of a 4-bit u p / d o w n binary ripple c o u n t e r using T flip flops. (10)

(ii) R e d u c e t h e n u m b e r of states in t h e following state table a n d tabulate the state

Starting f r o m state a a n d the input s e q u e n c e 0-1100010001, d e t e r m i n e the

14. a) For t h e t w o - i n p u t , t w o - o u t p u t s y s t e m , w h o s e primitive f l o w table is s h o w n below,

b) (i) A n a s y n c h r o n o u s sequential circuit is described by t h e excitation function

D r a w t h e logic d i a g r a m of t h e circuit. (2)

(ii) W h a t is a static h a z a r d ? Discuss with e x a m p l e s .

15. a) (i) Give t h e logic d i a g r a m of a basic R A M cell a n d d i s c u s s .

(ii) A 12-bit H a m m i n g code w o r d containing 8 bits of d a t a a n d 4 parity bits is r e a d

b) (i) Discuss t h e construction of a typical R O M . (10)

(ii) S h o w h o w t h e following functions c a n b e i m p l e m e n t e d using a PLA: (6)

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