INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT138
3-to-8 line decoder/demultiplexer;
inverting
Product specification September 1993
File under Integrated Circuits, IC06
Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

FEATURES The 74HC/HCT138 decoders accept three binary

weighted address inputs (A0, A1, A2) and when enabled,
• Demultiplexing capability
provide 8 mutually exclusive active LOW outputs (Y0 to
• Multiple input enable for easy expansion Y7).
• Ideal for memory chip select decoding The “138” features three enable inputs: two active LOW
(E1 and E2) and one active HIGH (E3). Every output will be
• Active LOW mutually exclusive outputs
HIGH unless E1 and E2 are LOW and E3 is HIGH.
• Output capability: standard
This multiple enable function allows easy parallel
• ICC category: MSI expansion of the “138” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “138” ICs and one inverter.

GENERAL DESCRIPTION The ”138” can be used as an eight output demultiplexer by

using one of the active LOW enable inputs as the data
The 74HC/HCT138 are high-speed Si-gate CMOS devices input and the remaining enable inputs as strobes. Unused
and are pin compatible with low power Schottky TTL enable inputs must be permanently tied to their
(LSTTL). They are specified in compliance with JEDEC appropriate active HIGH or LOW state.
standard no. 7A.
The ”138” is identical to the “238” but has inverting outputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
propagation delay CL = 15 pF; VCC = 5 V
tPHL/ tPLH An to Yn 12 17 ns
tPHL/ tPLH E3 to Yn 14 19 ns
En to Yn
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 67 67 pF

Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.

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Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 2, 3 A0 to A2 address inputs
4, 5 E1, E2 enable inputs (active LOW)
6 E3 enable input (active HIGH)
8 GND ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7 outputs (active LOW)
16 VCC positive supply voltage

handbook, halfpage
1 A0 Y0 15

2 A1 Y1 14

3 A2 Y2 13

Y3 12

Y4 11

E1 Y5 10
4
5 E2 Y6 9
6 E3 Y7 7

MLB312

Fig.1 Pin configuration. Fig.2 Logic symbol.

(a) (b)

Fig.3 IEC logic symbol. Fig.4 Functional diagram.

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Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

FUNCTION TABLE

INPUTS OUTPUTS
E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L

Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care

Fig.5 Logic diagram.

September 1993 4
Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (°C) TEST CONDITIONS

74HC
SYMBOL PARAMETER UNIT VCC WAVEFORMS
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
41 150 190 225 2.0
propagation delay
tPHL/ tPLH 15 30 38 45 ns 4.5 Fig.6
An to Yn
12 26 33 38 6.0
47 150 190 225 2.0
propagation delay
tPHL/ tPLH 17 30 38 45 ns 4.5 Fig.6
E3 to Yn
14 26 33 38 6.0
47 150 190 225 2.0
propagation delay
tPHL/ tPLH 17 30 38 45 ns 4.5 Fig.7
En to Yn
14 26 33 38 6.0
19 75 95 110 2.0
output transition
tTHL/ tTLH 7 15 19 22 ns 4.5 Figs 6 and 7
time
6 13 16 19 6.0

September 1993 5
Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To
determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

An 1.50
En 1.25
E3 1.00

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (°C) TEST CONDITIONS

74HCT
SYMBOL PARAMETER UNIT VCC WAVEFORMS
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
propagation delay
tPHL/ tPLH 20 35 44 53 ns 4.5 Fig.6
An to Yn
propagation delay
tPHL/ tPLH 18 40 50 60 ns 4.5 Fig.6
E3 to Yn
propagation delay
tPHL/ tPLH 19 40 50 60 ns 4.5 Fig.7
En to Yn
output transition
tTHL/ tTLH 7 15 19 22 ns 4.5 Figs 6 and 7
time

September 1993 6
Philips Semiconductors Product specification

3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

AC WAVEFORMS

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and
the output transition times.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition
times.

PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

September 1993 7