Quad 2-Input AND Gate: KK74HC08A
Quad 2-Input AND Gate: KK74HC08A
Quad 2-Input AND Gate: KK74HC08A
KK74HC08A
The KK74HC08A is identical in pinout to the LS/ALS08. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION KK74HC08AN Plastic KK74HC08AD SOIC TA = -55 to 125 C for all packages
FUNCTION TABLE
Inputs A L L H H B L H L H Output Y L L L H
KK74HC08A
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP** SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
KK74HC08A
VIH
Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage
VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0
VIL
VOH
VOL
VIN= VIH or VIL IOUT 20 A VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA
IIN ICC
KK74HC08A
tPLH, tPHL
Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance Power Dissipation Capacitance (Per Gate)
95 19 16 95 19 16 10
110 22 19 110 22 19 10
ns
tTLH, tTHL
ns
CIN
pF
TA=25C,VCC=5.0 V 20 pF
CPD
KK74HC08A
A 14 8 B 1 7
Dimension, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 10 3.81 8.26 0.36 0.56 1.78
D F
G H
H J
J K L M N
NOTES: 1. Dimensions A, B do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
A 14
Symbol A
MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0 0.1 0.19 5.8 0.25
B C
7 C R x 45
D F G
SEATING PLANE
H
J F M
J K M P R
NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side.