The SL74HCT138 is a 1-of-8 decoder/demultiplexer chip that decodes a 3-bit address input to select one of eight output lines. It has three chip select inputs - two active-low and one active-high - that can be used to cascade, demultiplex, or select chips. The device directly interfaces with CMOS, NMOS, and TTL components and operates over a voltage range of 4.5-5.5V with low input current of 1.0μA.
The SL74HCT138 is a 1-of-8 decoder/demultiplexer chip that decodes a 3-bit address input to select one of eight output lines. It has three chip select inputs - two active-low and one active-high - that can be used to cascade, demultiplex, or select chips. The device directly interfaces with CMOS, NMOS, and TTL components and operates over a voltage range of 4.5-5.5V with low input current of 1.0μA.
The SL74HCT138 is a 1-of-8 decoder/demultiplexer chip that decodes a 3-bit address input to select one of eight output lines. It has three chip select inputs - two active-low and one active-high - that can be used to cascade, demultiplex, or select chips. The device directly interfaces with CMOS, NMOS, and TTL components and operates over a voltage range of 4.5-5.5V with low input current of 1.0μA.
The SL74HCT138 is a 1-of-8 decoder/demultiplexer chip that decodes a 3-bit address input to select one of eight output lines. It has three chip select inputs - two active-low and one active-high - that can be used to cascade, demultiplex, or select chips. The device directly interfaces with CMOS, NMOS, and TTL components and operates over a voltage range of 4.5-5.5V with low input current of 1.0μA.
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SL74HCT138
1- of-8 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS The SL74HCT138 is identical in pinout to the LS/ALS138. The SL74HCT138 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The SL74HCT138 decodes a three-bit Address to one-of-eight active-lot outputs. This device features three Chip Select inputs, two active-low and one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states. TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A
ORDERING INFORMATION SL74HCT138N Plastic SL74HCT138D SOIC TA = -55 to 125 C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE Inputs CS1 CS2 CS3 X X H X H X L X X PIN 16 =VCC PIN 8 = GND H H H H H H H H L L L L L L L L L L L L L L L L A2 A1 A0 X X X X X X X X X L L L L L H L H L L H H H L L H L H H H L H H H Outputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H H H H H H H H H H H H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H H H H H H H H H
L H H H H L H H H H L H H H H L
H = high level (steady state) L = low level (steady state) X = dont care
SLS
System Logic Semiconductor
SL74HCT138
MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL *
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 2) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open.
SLS
System Logic Semiconductor
SL74HCT138
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 4.0 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 40 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 1.0 160 A A V Unit
VIH VIL VOH
Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage
VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA
4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5
V V V
VOL
Maximum Low-Level Output Voltage
VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA
IIN ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current
VIN=VCC or GND VIN=VCC or GND IOUT=0A VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0A
ICC
-55C
25C to 125C 2.4
mA
5.5
2.9
SLS
System Logic Semiconductor
SL74HCT138
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V, CL=50pF,Input t r=t f=6.0 ns)
Guaranteed Limit Symbol tPLH, t PHL tPLH, t PHL tPLH, t PHL tTLH, t THL CIN Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 4) Maximum Propagation Delay , CS1 to Output Y (Figures 2 and 4) Maximum Output Transition Time , CS2 or CS3 to Output Y (Figures 3 and 4) Maximum Output Transition Time, Any Output (Figures 2 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Enabled Output) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 25 C to -55C 30 27 30 15 10 85C 38 34 38 19 10 125C 45 41 45 22 10 Unit ns ns ns ns pF
