Designing an ALU 1 Introduction

An ALU (arithmetic-logic unit) is the center core of each central processing unit. It consists of purely combinational logic circuits and performs a set of arithmetic and logic micro operations on two input busses. It has n encoded inputs for selecting which operation to perform. The select lines are decoded within the ALU to provide up to n different operations. The ALU we will be building will be capable of up to !" different operations.

2 Methodology
2.1 Operations of our ALU #" #$ # #! #% &in 'peration (unction Arithmetic Unit % % % % % % )*+A Transfer A % % % % % ! )*+A,! Increment A % % % % ! % )*+A,Addition % % % % ! ! )*+A,-,! Add with carry % % % ! % % )*+A,.A plus !/s comp. of % % % ! % ! )*+A,.-,! #ubtraction % % % ! ! % )*+A-! 0ecrement A % % % ! ! ! )*+A Transfer A Logic Unit % % ! % % % )*+A and - A10 % % ! % ! % )*+A or '2 % % ! ! % % )*+A 3or - 4'2 % % ! ! ! % )*+.A &omplement A #hifter % % % % % % )*+A Transfer A % ! % % % % )*+shl A #hift left A ! % % % % % )*+shr A #hift right A ! ! % % % % )*+% Transfer %/s Implementation Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Logic Unit Logic Unit Logic Unit Logic Unit #hifter Unit #hifter Unit #hifter Unit #hifter Unit

2.1.1 Explanation of select operations of our ALU 5ost of these functions will probably be in good memory to you6 7ust to point out some that you might have forgotten8 )*+ A,.-,! we need the one/s complement of - to A and add !. According to the table this is e9uivalent to subtracting - from A. :hy does this wor;< 2emember how the !/s complement of a number is computed6 it is8 n-!-that number. -y adding the !6 we thus get A , complement of - here6 which e9uals A = -. )*+shl A >ust as a reminder here6 in case you forgot6 to shift left means that every bit is from to n to n,!6 which e9uals ta;ing the original number ? )*+shr A -asically the opposite of what is happening on a left shift6 each number is shifted from n to n-!6 this e9uals a division by . 2.1.2 ALU Number format )ou might now thin;6 that an important 9uestion to decide when building this state machine is which number format to use6 i.e. unsigned6 one/s complement6 two/s complement. :ell6 not really. A state machine that can handle unsigned numbers will also handle 7ust as well two/s complement numbers because6 as you can either recall or can loo; up6 adding.subtracting is done e3actly the same way for two/s complement and for unsigned numbers. The only difference is in the interpretation of the number6 i.e. the number !%%! will mean @ if we are in an unsigned system6 it will mean =A if we are in a "-bit two/s complement system. #o6 it is highly recommendable to wor; with an Bunsigned/ ALU6 especially as in that way you can basically double the positive numbers available to you but6 pay attention to what your numbers mean. 2.2 Modeling the ALU

2.2.1 Software-View of ALU This whole table could be modeled using a single case statement6 however its synthesiCed structure would be poor then. Instead6 the ALU has been modeled with a separate arithmetic unit6 logic unit and shifter as indicated by the circuit structure below. This modulariCation is closer to reality6 ma;es it easier to follow the processes and produces better pre-optimiCed timing.

#D"8%E

#D!8%E

#D E

#D"8$E

AD$8%E

Logic Unit

Logic UnitD$8%E ALUF 1o#hift DA8%E )D$8%E

-D$8%E

5U4

#hifter

Arithmetic Unit

&arry-In

Arith UnitD$8%E

This here is already a very advanced6 software-oriented model of the ALU as we loo; at it right from the start as a four bit ALU 2.2.2 Hardware-View of ALU If we would be loo;ing at it from a hardware perspective6 we would have to consider every bit separately in a socalled bit slice. The ALU itself would then be built from an appropriate number of these bit slices which implies a very stringent limit on performance due to the propagation of carries among the ALU stages. Gere as an e3ample hardware schematic of an ALU with two select inputs and one mode input (i.e. three select inputs) that supports the following operations8 #! % % ! ! % % ! ! % % ! ! #% % ! % ! % ! % ! % ! % ! 5 &arry % % % % ! ! ! ! ! ! ! ! 4 4 4 4 % % % % ! ! ! ! (unction Logic 'perations )*+A )*+.A )*+A 4'2 )*+A 41'2 Arithmetic 'perations with &arry + % )*+A )*+.A )*+A,)*+.A,Arithmetic 'perations with &arry + ! )*+A,! )*+.A,! )*+A,-,! )*+.A,-,! &omment Transfer &omplement A 4'2 A 41'2 Transfer &omplement #um A and #um of - and complement A Transfer with &arry Two/s complement of A Add with carry #ubtraction

This is now one bit slice that would enable us to build an ALU with the functions described above. To get an ALU with four bits6 we would have to logically connect four of these6 for an eight bit ALU eight of these which would certainly amount to 9uite some wor; and would also enable numerous errors. Using a software-oriented approach such as with the Altera -oard thus simplifies designs li;e these e3tremely. 2.2. !esi"nin" t#e ALU in Software :hen starting this design it will be most helpful to us if we first loo; separately at all components of the ALU. 2.2.3.1 Logic Unit Let/s start with the Logic Unit. The Logic Unit has as input A and - as well as two of the selector bits. These decide which of the four functions and6 or6 3or6 complement will be used. This is e3tremely easy6 as the functions A106 '26 4'2 and 1'T are part of the standard HG0L used in 5a3,plusII6 a simple case statement will thus be enough here. 2.2.3.2 Arithmetic Unit The same logic as applied for the logic unit can also be used for the Arithmetic Unit. The data inputs are again A and -6 as selectors #%6 #! and the &arry-In -it are used. B,/6 B-B and Bnot/ as functions should be enough to implement this bloc;. 2.2.3.3 Multiplexer The outputs from these units are then fed into a 5u36 which based on # will decide which of its inputs will be fed to the #hifter. 2.2.3.4 Shifter -ased on #" and #$6 the shifter will then either send the input through unchanged or shift it appropriately. #hould you not be aware of the HG0L-synta3 needed for shifting a shiftregister6 you can also help yourself by declaring two help registers. In these you can copy the appropriate parts of the original register and fill up the remainder-cell with Ceros.

2.3 Working with the Altera Software :e have now covered the basic design steps involved in this lab6 so that you should be able to come up with a basic layout of the program and can start writing the HG0L code. :hen starting to write the program go to the Bassign/ menu6 Bdevice/ and select as family B5A4A%%%#/ and the IJ5A! K#L&K"-A as device. After you have done that and saved your file for the first time6 an .acf file will have been created. 'pen up the file and in the first begin-end bloc; (it should also contain the information about your device) enter your io- terms and the pins you want to assign to them. Gere an e3cerpt to show the synta3.
BEGIN !B1"#EB$UN%E#"S&N%"$U' ( !B1"$U' ( !IN ) ,-+ SL$."%L$%/"$U' ( !IN ) 40+ !B1"SINGLE"!ULSE ( !IN ) 41+ #E2I%E ) E!M3121SL%1443+ EN#+ !IN ) 4*+

)ou also have to pay attention to the fact that a lot of the pins on the chip are already preassigned6 e.g. for connections to the >TAL-programming header6 or for Hcc and Lround. (&hec; your Altera University Jac;age User Luide) To ma;e sure that you are not accidentially assigning an output to any one of these pins6 after compiling your pro7ect6 chec; the ?.rpt file that will be created. #hould any of the pins have two terms assigned to them6 you have to change your pinassignments. (This is also why we assign the pins manually. :hen we assign them automatically6 sometimes unluc;ily double assignments occur that might cause problems)
R R R R R R R R R E E E E E E E E E S S S S S S S V S S L E E E E E E E C R C E E S V L L L R R R R R R R C E L R R B C S S S V V V V G V V V I G S G O G V V _ C B B B E E E E N E E E N N E N C N E E d I _ _ _ D D D D D D D D T D T D K D D D p O g e f -----------------------------------------------------------------_ / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 | | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 65 | | 22 EPM7128SLC84-7 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|

RESERVED VCCIO #TDI RESERVED RESERVED RESERVED RESERVED GND RESERVED RESERVED RESERVED #TMS RESERVED RESERVED VCCIO RESERVED RESERVED RESERVED RESERVED RESERVED GND

LSB_d LSB_c GND #TDO LSB_b LSB_a MSB_dp MSB_g VCCIO MSB_f MSB_e MSB_d #TCK MSB_c MSB_b GND MSB_a RESERVED RESERVED RESERVED RESERVED Pin

Figure 1. Pin Assignment table in *.rpt-file

This is an e3ample of the chip-pin picture that is included in the ?.rpt file. Jlease pay attention here to the fact that pin is not L10 as shown in the Altera 0ocumentation6 pin " is L10. It is adviseable6 that you always use pin " to connect ground to in case you are wor;ing with the Logic analyCer. To visualiCe the output we will be using the seven segment display of the 5A4-chip. The easiest way to do this is to create one register of length ". This registers can at ma3.

e3press !M different numbers6 this is also the ma3. amount of numbers that can be e3pressed on a single A-#egment-0isplay when using the Ge3 number system and it is also the ma3 number that we might want to output. The ne3t thing that needs to be done is that you define the content of a register of length seven that stands for the seven segments of the 0isplay6 based on the four-bit register. After this has been done6 ta;e a loo; in the Altera user guide to find out which output pins are connected to which segment and assign appropriate output terms to them. Attention8 The Altera &A0-software is set to a default value that will compile your program in such a way that it will try to optimiCe both speed and the area in the chip (ie spread out the logic a bit). :hen you try to compile this program you must set the compilation to optimiCe the use of the chip as your design will otherwise not fit on it. )ou do this by going to BAssign/ and then BLlobal Jro7ect Logic #ynthesis/. In the window that will subse9uently pop up6 move the indicator between Area and #peed all the way to Area and set B5ulti-Level #ynthesis for 5a3N%%%.A%%% design/ to yes. If this does not ma;e enough space available on the chip for your design6 ta;e another loo; at your e9uations. )ou will probably have a lot of additions in them. (or each of these additions 5a3,plusII will create a new adder and thus waste a lot of space. To avoid this6 use the generic form A,4 and then have another case statement that decides what 4 is (- or -,! orO.) 2. .1 Simulation 1ow your program is compiled6 to ma;e sure that it does what you want it to do6 you need to simulate it. (And you need the simulation to get chec;ed off) To do this6 you must have compiled your HG0L-file6 and you must have the pro7ect set to it. If you go to the B(ile/-menu6 select Bnew/ and then the B.scf/ e3tension6 a new waveform file will be created for you. 5a;e sure that you select appropriate values for the end time in the Bfile/-menu and for the grid siCe in the Boptions/-menu. 1ow go to BInter 1odes from #1(/ in the Bnodes/ menu. After you applied the Blist/ command all io nodes in your file should be shown and you can select these that you want displayed in your simulation file. Jress B'P/ to continue. 1ow you should be in the default setup of the simulator file. The ne3t thing is to create a meaningful waveform. Gighlighting the node6 you can use one of the buttons on the right-hand side of the screen to change the entire waveform to !6%6 cloc; etc.

)ou can however also highlight a channel go to BUtilities/ -Q #election and select a certain time interval that is to be changed. That way you can e.g. simulate changing one of the dip-switches for a certain time. Gere is a sample simulation6 please don/t ta;e this as a literal e3ample. There are other inputs.outputs that might be important to you.

Figure 2. Sample Simulation Waveform file

2. .2 $ro"rammin" t#e %ax-&#ip :hen programming6 be sure that you are programming the right chip on the board. )ou select these through the on-board 7umpers. Ta;e a loo; in the Altera User Luide for the correct configuration. Also6 chec; BGardware #etup/ in the B'ptions/ menu to ma;e sure that you are writing to LJT . )ou are now ready to program. &onnect your Altera-board with the byteblaster cable that should be included in the bo3 to LJT and hoo; up the power supply. The 5A4-chip is an IIJ2'56 which means it is erasable and programmable however6 it will ;eep its programming until you reprogram it6 so you can conviniently program it in the computer room and then ta;e it outside to connect it to one of the Logic AnalyCers. To program the chip6 go to the B5a3,plus II/ menu and select the programmer. &hec; the output that appears on the screen especially the device. If everything is o;ay6 press program. 1ow you can try out your programmed chip6 to see if it behaves as e3pected. 2.4 How ou !an get "ore out of our ALU

2.'.1 &arr(-)ut and )*erflow As we already discussed at the beginning of this tutorial6 it is advantageous to act as if your ALU would only deal with unsigned numbers as that way you can also deal with two/s complement numbers. Gowever6 there are now two conditions that can mess us up in these systems6 carry-out and overflow.

2.'.2 &arr(-)ut :hat is a carry-out (7ust in case you don/t remember )< :ell6 the highest number we can display on the A-#egment display is B(/ which symboliCes !N. :e get this number for e3ample 7ust by setting all A-switches high when all selection switches and the carry-in switch are low. :hat happens now if we set the carry-in high6 too< Up to now the output register was8 B!!!!/. Adding another one now will set it to B%%%%/ and we would have a ! in the fifth position. As this position however does not e3ist6 this number = our carry-out = is lost. #o6 what can we do< :ell6 9uite easy6 we can increase the register. Gowever6 then we cannot anymore display all the numbers the register can contain on the A-segment display. To ta;e care of that6 we can use the decimal point of the A-#egment display to show if we have a carry-out or not and thus we can now display numbers from % to $! instead of only from % to !N. 2.'. )*erflow &arry-out does of course only ma;e sense when we are dealing with unsigned numbers6 when we deal with two/s complement numbers we might get overflow which basically means that our result will have the wrong sign. To e3emplify this6 assume that you are adding the numbers !%%! and !%!! in "-bit two/s complement. This means of course6 that both numbers are negative6 but what is the result here< %!%%6 a positive number6 which is a completely wrong result. There are now several ways to test for overflow however6 the easiest one is to follow the rule8 B:hen the two numbers coming in6 have the same signbit6 and the number going out has a different one6 then overflow has occurred/. Iasy6 isn/t it< (And wor;s in @@.@@@..R of all cases a +Q good enough for what we do at the moment) )ou can implement this6 using the other decimal point on the system however6 as already stated at the beginning6 always pay attention now to the interpretation of your output. &arry-out is meaningless for signed numbers and overflow for unsigned numbersS