UNIVERSITI MALAYSIA PERLIS

SCHOOL OF MICROELECTRONIC ENGINEERING

EMT 353- DIGITAL IC DESIGN

GROUP MEMBERS

MATRIC NUMBER

ZAKARIA BIN ISHAK

121012545

MUHAMMAD AMIRUL ASYRAF BIN ABDUL PATAH

121012734

LECTURE'S NAME : DR. NAZRIN BIN MD. ISA

Introduction Traffic lights, also known as traffic signals, traffic lamps, signal lights and robots. This devices are positioned at or near road junctions, pedestrian crossing and other locations to control competing flows of traffic. It were first installed in 1868 in London, United Kingdom. Traffic lights alternate the right on way accorded to road users by displaying lights of a standard color (red, yellow, and green) following a universal color.

State Table:

Traffic Light States S0 (0000) S1 (0001) S2 (0010) S3 (0011) S4 (0100) S5 (0101) S6 (0110) S7 (0111) S8 (1000) S9 (1001) S10 (1010) S11 (1011)

TFA

TFB

TFC SouthEast/NorthWest Red Red Red Red Red Red Green Yellow Red Red Red Red

TFD West-South/EastNorth Red Red Red Red Red Red Red Red Red Green Yellow Red Delay 30 sec 3 sec 3 sec 30 sec 3 sec 3 sec 30 sec 3 sec 3 sec 30 sec 3 sec 3 sec

NorthWestSouth/SouthEast/East-West North Green Red Yellow Red Red Red Red Green Red Yellow Red Red Red Red Red Red Red Red Red Red Red Red Red Red

State Diagram:
30 seconds 3 seconds
State 11, A=RED B=RED C=RED D=RED State 0, A=GREEN B=RED C=RED D=RED

3 seconds
State 1, A=YELLOW B=RED C=RED D=RED

3 seconds

State 10, A=RED B=RED C=YELLOW D=RED

3 seconds

30 seconds
State 9, A=RED B=RED C=GREEN D=RED

State 2, A=RED B=RED C=RED D=RED

30 seconds

State 3, A=RED B=GREEN C=RED D=RED

3 seconds
State 8, A=RED B=RED C=RED D=RED

3 seconds
State 4, A=RED B=YELLOW C=RED D=RED State 7, A=RED B=RED C=RED D=YELLOW

3 seconds

State 6, A=RED B=RED C=RED D=GREEN

State 5, A=RED B=RED C=RED D=RED

3 seconds

30 seconds

HDL Coding and Parameterizable module TL4J ( input wire clk, input wire clr, output [11:0] lights, output reg [3:0] TLA,TLB,TLC,TLD ); reg [2:0] TL; reg [3:0] state; reg [8:0] count; assign lights = state; parameter s0=4'b0000, s1=4'b0001, s2=4'b0010, s3=4'b0011, s4=4'b0100, s5=4'b0101, s6=4'b0110,s7=4'b0111,s8=4'b1000,s9=4'b1001,s10=4'b1010,s11=4'b1011 ; parameter SEC30 = 9'b100101011, SEC3 = 5'b11101; parameter Green =2'b00, Yellow = 2'b01, Red = 2'b10; always @ (posedge clk or posedge clr ) begin if (clr==1) begin state <= s0; count <= 0; end else case (state) s0 : if (count < SEC30) begin state <= s0; count <= count + 1; end else begin state <= s1; count <= 0; end s1 : if (count < SEC3) begin state <= s1;

count <= count + 1; end else begin state <= s2; count <= 0; end s2 : if (count < SEC3) begin state <= s2; count <= count + 1; end else begin state <= s3; count <= 0; end s3 : if (count < SEC30) begin state <= s3; count <= count + 1; end else begin state <= s4; count <= 0; end s4 : if (count < SEC3) begin state <= s4; count <= count + 1; end else begin state <= s5; count <= 0; end s5 : if (count < SEC3) begin state <= s5; count <= count + 1; end

else begin state <= s6; count <= 0; end s6 : if (count < SEC30) begin state <= s6; count <= count + 1; end else begin state <= s7; count <= 0; end s7 : if (count < SEC3) begin state <= s7; count <= count + 1; end else begin state <= s8; count <= 0; end s8 : if (count < SEC3) begin state <= s8; count <= count + 1; end else begin state <= s9; count <= 0; end s9 : if (count < SEC30) begin state <= s9; count <= count + 1; end else begin

state <= s10; count <= 0; end s10 : if (count < SEC3) begin state <= s10; count <= count + 1; end else begin state <= s11; count <= 0; end s11 : if (count < SEC3) begin state <= s11; count <= count + 1; end else begin state <= s0; count <= 0; end default state <= s0; endcase end always @ (*) begin case (state) s0 : begin TLA = Green; TLB = Red; TLC = Red; TLD = Red; end s1 : begin TLA = Yellow; TLB = Red; TLC = Red; TLD = Red; end

s2 : begin TLA = Red; TLB = Red; TLC = Red; TLD = Red; end s3 : begin TLA = Red; TLB = Green; TLC = Red; TLD = Red; end s4 : begin TLA = Red; TLB = Yellow; TLC = Red; TLD = Red; end s5 : begin TLA = Red; TLB = Red; TLC = Red; TLD = Red; end s6 : begin TLA = Red; TLB = Red; TLC = Green; TLD = Red; end s7 : begin TLA = Red; TLB = Red; TLC = Yellow; TLD = Red; end s8 : begin TLA = Red; TLB = Red; TLC = Red;

TLD = Red; end s9 : begin TLA = Red; TLB = Red; TLC = Red; TLD = Green; end s10 : begin TLA = Red; TLB = Red; TLC = Red; TLD = Yellow; end s11 : begin TLA = Red; TLB = Red; TLC = Red; TLD = Red; end default : begin TLA = Yellow; TLB = Yellow; TLC = Yellow; TLD = Yellow; end endcase end endmodule

Testbench in verilog HDL module TL4J_tb (); reg clk,clr; wire [3:0] lights ; wire [3:0] TLA,TLB,TLC,TLD ; parameter half_cycle = 50; initial begin clk=0; forever #half_cycle clk = ~ clk; end initial begin clr = 1; #half_cycle; clr = 0; end TL4J inst_TL4J (clk,clr,lights,TLA,TLB,TLC,TLD); endmodule

Waveform Explanation

Figure 1. Full state

Figure 1 above shows the waveform of the full state of our traffic light design consist of State0 to State11. The wave produced from State 0 to State 11 are repeated when it reach from the initial state (State0) to the final state (State11). The following parameter from the waveform are given: Traffic Light Colors in Binary in Binary 1. Green = 00 2. Yellow = 01 3. Red = 10 Traffic Light 1. 2. 3. 4. TLA = Traffic light A (North-South/South-North) TLB = Traffic light B (West-East/East-West) TLC = Traffic light C (South-East/North-West) TLD = Traffic light D (West-South/East-North)

At State0(0000)

Figure 2.0. State0 Figure above shows the condition of the waveform at State0 (0000). Traffic Light A(TLA) will display 00(Green) for 30 seconds and making the others Traffic Light B(TLB), Traffic Light C(TLC) and Traffic Light D(TLD) display 10(Red) also for 30 seconds.

Figure 2.1. State0 Condition

At State1 (0001)

Figure 3. State1 At the Figure 3 above the TLA will display 01(Yellow) at State1 (0001) for 3 seconds. The other traffic lights TLB, TLC and TLD remain 10(Red) for 3 seconds.

At State2 (0010)

Figure 4. State2 Figure above show that the TLA become 10(Red) at State2 (0010) for 3 seconds. The other traffic lights TLB, TLC and TLD remain 10(Red) for 3 seconds.

At State3 (0011)

Figure 5.0. State3 At this state, State3 (0011), TLB turns 00(Green) while others TLA, TLC and TLB at 10(Red) and remain for 30 seconds shown in Figure 5.1.

Figure 5.1. State3 condition

At State4 (0100)

Figure 6. State4 During this state, State4 (0100), TLB is at 01(Yellow) for 3 seconds and other traffic lights TLA, TLC and TLD at 10(Red) also for 3 seconds as shown in Figure 6 above.

At State5 (0101)

Figure 7. State5 At State5 (0101), all traffic lights TLA, TLB, TLC and TLD are at 10(Red) for 3 seconds. This can be refers at the Figure 7.

At State 6(0110)

Figure 8.0. State6 From the Figure 8.0 above, TLC displays 00(Green) for 30 seconds and others TLA, TLC and TLD displays 10(Red) also for 30 seconds.

Figure 8.1 State6 condition

At State7 (0111)

Figure 9. State7 At the Figure above the TLC will display 01(Yellow) at State7 (0111) for 3 seconds. The other traffic lights TLA, TLB and TLD remain 10(Red) for 3 seconds.

At State8 (1000)

Figure 10. State8 At State8 (1000), all traffic lights TLA, TLB, TLC and TLD are at 10(Red) for 3 seconds once more. This can be refers at the Figure 10.

At state9 (1001)

Figure 11.0. State9 From the Figure 11.0 at State9 (1001) above, TLD displays 00(Green) for 30 seconds and others TLA, TLB and TLC displays 10(Red) also for 30 seconds.

Figure 11.1. State9 condition

At State10 (1010)

Figure 12. State10 At the Figure above the TLD will display 01(Yellow) at State10 (0001) for 3 seconds. The other traffic lights TLA, TLB and TLC remain 10(Red) for 3 seconds.

At State11 (1011)

Figure 13. State11 Figure 13 above shows the final state of the waveform at State11. The TLD along with TLA, TLB and TLC display 10(Red) for 30 seconds before goes back to the initial state0.

RTL Diagram
Selector12

s tate WideOr0
s0 s1 s2 SEL[11..0] s3 s4 clk s5 reset s6 Q count[8..0] s7 SEL 9' h000 -DATAA OUT0 DATAB s10 s11 MUX21 DATA[11..0] 8' h00 -s9 s8

count[8..0] count~[8..0]
OUT D PRE

WideOr1

Add0
A[8..0] B[8..0]

9' h001 --

+
Les s Than0 ADDER

A[8..0] B[8..0]

WideOr2

9' h12B --

<
LESS_THAN

lights [11..0]

Les s Than1
A[8..0] B[8..0]

ENA CLR

9' h01D --

<
LESS_THAN 9' h000 --

count~[17..9]
SEL DATAA OUT0 DATAB

SELECTOR

WideOr3 Selector13

TLD~0
MUX21 2' h0 --

TLD[3..0]
SEL[11..0]

TLC~0
2' h0 --

TLC[3..0] TLB~0
OUT 2' h0 --

TLB[3..0] TLA~0
2' h0 --

TLA[3..0]
DATA[11..0]

SELECTOR

Selector14

SEL[11..0]

OUT

DATA[11..0]

SELECTOR

Selector15

SEL[11..0]

OUT

DATA[11..0]

SELECTOR

Selector16

SEL[11..0]

OUT

DATA[11..0]

SELECTOR

Selector17

SEL[11..0]

OUT

DATA[11..0]

SELECTOR

Selector18

SEL[11..0]

OUT

DATA[11..0]

SELECTOR

Selector19

SEL[11..0]

OUT

DATA[11..0]

SELECTOR

Selector20

SEL[11..0]

OUT

DATA[11..0]

SELECTOR

clk clr

LessThan0~2
DATAA DATAA

Selector6~0 state.s6
COMBOUT DATAC PRE D Q DATAA COMBOUT DATAB

count[8]~47 count[8]
PRE COMBOUT DATAA LOGIC_CELL_COMB (EAFF) LOGIC_CELL_COMB (F888) LOGIC_CELL_COMB (A5A5) !CLR SCLR SDATA DATAB COMBOUT DATAC DATAD DATAD DATAD ENA LOGIC_CELL_COMB (22F2) !CLR !CLR LOGIC_CELL_COMB (000F) COMBOUT DATAC DATAD LOGIC_CELL_COMB (FEFF) LOGIC_CELL_COMB (FF75) COMBOUT DATAA DATAD ENA LOGIC_CELL_COMB (0003) SCLR SDATA SLOAD !CLR !CLR LOGIC_CELL_COMB (000A) DATAC DATAD LOGIC_CELL_COMB (FEFF) ENA DATAD DATAB COMBOUT DATAB !CLR LOGIC_CELL_COMB (FEFF) DATAA !CLR !CLR DATAD !CLR !CLR !CLR !CLR ENA LOGIC_CELL_COMB (F888) LOGIC_CELL_COMB (31F5) COMBOUT DATAD ENA LOGIC_CELL_COMB (22F2) ENA LOGIC_CELL_COMB (222F) DATAC LOGIC_CELL_COMB (2A3F) SLOAD SLOAD ENA ENA DATAD ENA DATAC !CLR DATAD COMBOUT DATAD SDATA SDATA DATAC DATAC COMBOUT DATAC DATAC DATAB LOGIC_CELL_COMB (A50A) LOGIC_CELL_COMB (A50A) LOGIC_CELL_COMB (F888) SCLR ENA SCLR COMBOUT DATAB COMBOUT DATAA COMBOUT 1 DATAD 1 DATAD LOGIC_CELL_COMB (0003) DATAD LOGIC_CELL_COMB (22F2) !CLR SLOAD COMBOUT DATAC DATAB PRE D Q PRE D Q PRE D Q PRE D Q DATAA ENA DATAA DATAA 1 DATAD 1 DATAD ENA DATAB LOGIC_CELL_COMB (55AA) LOGIC_CELL_COMB (5A5F) COUT LOGIC_CELL_COMB (5A5F) COUT LOGIC_CELL_COMB (5A5F) DATAD ENA DATAA DATAA ENA DATAD DATAC COMBOUT 1 DATAD COMBOUT 1 DATAD COMBOUT D Q DATAC COUT COUT CIN COUT CIN COUT DATAC COMBOUT DATAB PRE DATAA DATAA DATAB COMBOUT COMBOUT COMBOUT ENA CIN CIN COMBOUT CIN COMBOUT DATAB DATAA PRE D Q DATAD D Q DATAD DATAC DATAB CIN

WideOr3 state.s6_REGOUT
DATAB COMBOUT DATAD PRE D Q LOGIC_CELL_COMB (EEFF)

count[0] count[0]~27 LessThan1~0 state.s3

count[1]~29 count[2]~31 count[4]~35

count[3]~33 Selector3~0

count[5]~37

count[5] Selector4~0

state.s4

Selector7~0 state.s7
DATAB PRE D Q DATAB PRE D Q PRE D Q

Selector9~0 state.s8 WideOr2~0 LessThan1~2

Selector10~0 state.s9
DATAA DATAA

state.s10 state.s0 count[8]~41

state.s11

Selector0~0 state.s1

Selector1~0

count[8]~42

2' h0 -

!CLR

TLA[0. 3] WideOr1
DATAA DATAB COMBOUT DATAC 2' h0 2' h0 -

Technology Map Diagram

count[2] count[7] LessThan0~1

TLC[0. 3]

PRE D Q

clk
PRE D Q

LessThan0~0

state.s2 WideOr3~0

TLD[0. 3] WideOr2
8' h00 -

ENA

DATAA

SCLR

DATAB

COMBOUT

SDATA

DATAC

SLOAD

DATAD

lights[0. 11]

!CLR

LOGIC_CELL_COMB (07FF)

clr

count[6]~43

CIN

state.s4_REGOUT
2' h0 -

COMBOUT

DATAA

count[7]~45

COUT

CIN

1 DATAD

COMBOUT

DATAA

TLB[0. 3]

LOGIC_CELL_COMB (A50A)

COUT

1 DATAD

state.s5

LOGIC_CELL_COMB (5A5F)

PRE

D Q

count[6]

PRE D Q

ENA

!CLR

ENA

state.s11_REGOUT state.s9_REGOUT state.s0_REGOUT state.s7_REGOUT state.s10_REGOUT state.s1_REGOUT

SCLR

count[1]

SDATA

PRE

D Q

SLOAD

!CLR

ENA

SCLR

SDATA

SLOAD

!CLR

count[3] count[3]_REGOUT

PRE D Q

ENA

SCLR

SDATA

SLOAD

!CLR

count[4] count[4]_REGOUT

PRE D Q

ENA

SCLR

SDATA

SLOAD

!CLR

state.s3_REGOUT

count[0]_REGOUT

state.s8_REGOUT

count[1]_REGOUT

TLB~0_COMBOUT TLC~0_COMBOUT TLD~0_COMBOUT TLA~0_COMBOUT count[8]~39_COMBOUT LessThan1~1_COMBOUT WideOr0_COMBOUT count[8]~40_COMBOUT

Generated State Diagram

s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11

Conclusion Traffic light is used to control the flow of vehicle. In the recent years, the need the transportation has gain immerse important for logistic as well as for common human. This has given rise to the number vehicle on the road. Due this reason, traffic jam and road accident are common sight in any busy city. So, the traffic light is design to give the solution for all the problem above. In our design, we have use a 4 traffic light to solve a problem of a 4 junction road that consist of North, West, South and East. Each traffic has been given its times to work sequentially such as North-South/South-North, West-East/East-West, North-West/South-East and EastNorth/West-South. The time given for each direction to allow cars to move (green light) are 30 seconds while for yellow and red light are 3 seconds delays.