P.G. Diploma Examination - 2010: (Vlsi Design)
P.G. Diploma Examination - 2010: (Vlsi Design)
P.G. Diploma Examination - 2010: (Vlsi Design)
7046
(20)
6. (a) Give the general Architecture of FPGA. (5) (b) Explain how a logic function can be implemented using gate array with an example. (15) 7. What is meant by Process in VHDL? Explain process. (i) using Variables; (ii) using Signals. (20)
8. (a) Design a full subtractor and write the VHDL code for a full substrater using logic equations. (14) (b) Write the VHDL description to design a D Flip Flop. (6) 9. (a) Explain the significance of timing simulation in the ASIC design flow. (b) Explain the Hazards and the method to eliminate it in the digital logic circuits. (10) (10)
10. Explain how the micro timing diagram is produced for the logic circuits with an examples. (20) %%%%%%