a31s datasheet v1.0 20130130 - for睿欣电子-2013-3-21

A31s
Datasheet
Revision 1.0
January 30, 2013
Declaration
Declaration
THIS A31s DATASHEET IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER
TECHNOLOGY (ALLWINNER). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE
WRITTEN APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT
OWNER.
THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE.

ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR
SPECIFICATIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY
RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR FOR ANY INFRINGEMENTS OF PATENTS OR
OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS
GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF
ALLWINNER. THIS DATASHEET NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND,
INCLUDING FITNESS FOR ANY PARTICULAR APPLICATION.
THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.

CUSTOMERS SHALL BE SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED THIRD
PARTY LICENCES. ALLWINNER SHALL NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN
RESPECT OF ANY REQUIRED THIRD PARTY LICENCE. ALLWINNER SHALL HAVE NO WARRANTY,
INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS COVERED UNDER ANY
REQUIRED THIRD PARTY LICENCE.
A31s Datasheet (Revision1.0)
Copyright 2013 Allwinner Technology. All Rights Reserved.
Page 2
Revision History
Revision History
Version
Date
1.0
2013.01.30
A31s Datasheet (Revision 1.0)
Author
Description
Initial Version
Page 3
Table of Contents
Table of Contents
Declaration ........................................................................................................................................................ 2
Revision History ............................................................................................................................................... 3
Table of Contents ............................................................................................................................................. 4
1
OVERVIEW ................................................................................................................................................. 5
FEATURES ................................................................................................................................................. 6
BLOCK DIAGRAM ................................................................................................................................... 10
PIN DESCRIPTION................................................................................................................................... 11
4.1.
Pin Characteristics ............................................................................................................................. 11
4.2.
GPIO Multiplexing Functions ............................................................................................................. 18
4.3.
Detailed Pin/Signal Description ......................................................................................................... 22
4.4.
Power/GND Signal Description ......................................................................................................... 27
ELECTRICAL CHARACTERISTICS ........................................................................................................ 29

5.1.
Absolute Maximum Ratings ............................................................................................................... 29
5.2.
Recommended Operating Conditions ............................................................................................... 29
5.3.
DC Electrical Characteristics ............................................................................................................. 30
5.4.
Oscillator Electrical Characteristics ................................................................................................... 30
5.5.
Power up AND Power Down Sequence ............................................................................................ 32
PIN ASSIGNMENT ................................................................................................................................... 33

6.1.
Ball map ............................................................................................................................................. 33
6.2.
Pin Dimension .................................................................................................................................... 34
Page 4
OVERVIEW
OVERVIEW
The Allwinner A31s processor is a quad-core phablet processor designed for the phablet market. The phablet
is a product category that combines the functionalities of a smartphone with that of a tablet, and its size
usually falls somewhere in between a smartphone and a tablet.
The A31s processor is based on quad-core Cortex-A7 CPU, which is the most power efficient processor
developed by ARM. It also comes with SGX544MP2 GPU with eight logic core to enable powerful 3D
computing capability as well as excellent UI experience, especially when it comes to the smoothness of
screens with large size.
More importantly, A31s processor integrates a robust Audio Codec that includes two sets of I2S/PCM
interface for Baseband and Bluetooth, two integrated differential analog MIC for headset and phone, as well
as a digital MIC. It is capable of 3G, 2G, LTE, WiFi, Bluetooth, FM, GPS, AGPS, NFC and other voice and
data wireless transmission technology with a minimum of external components.
Additionally, A31s processor provides a wide range of peripheral interfaces. For example, it integrates display
interfaces such as HDMI, RGB LCD and LVDS, image input interfaces such as CSI, and data interfaces such
as USB OTG, USB EHCI/OHCI, SDC, SPI, UART, etc.
When it comes to power efficiency, AXP221s is specially designed for the power optimization of A31s. A31s
processor also supports a smart Power Consumption Management System to dynamically adjust CPU
frequency and voltage, supports DRAM Dynamic Frequency Scaling technology to dynamically adjust DRAM
frequency based on bandwidth requirements, and also supports Super Standby Mode to lower the system
power consumption during system standby.
Page 5
FEATURES
FEATURES
GIC
QUAD-CORE CPU
Quad
Cortex-A7
ARMv7 ISA standard ARM instruction set plus
Thumb2, Jazeller RCT
NEON SIMD coprocessor and VFPv4 for each
CPU
TrustZone security technology
Hardware virtualization
Large Physical Address Extensions(LPAE)
Debug and trace features
One general timer for an individual CPU
32KB instruction and 32KB data L1 cache for an
individual CPU
Shared 1MB L2 cache
- Support 16 SGIs, 16 PPIs, and 128 SPIs

- Support ARM architecture security extensions
- Support ARM architecture virtualization
extensions
- Support uniprocessor and multiprocessor
environments
HS-Timer
- 4 channels
- Clock source fixed to AHB, and pre-scale ranges
from 1 to 16
- 56-bit counter that can be separated to 24-bit
high register and 32-bit low register
DMA
GRAPHIC ENGINE
3D
- PowerVR SGX544MP2 GPU

- Support OpenGL ES 2.0, OpenVG 1.1, OpenCL
1.1, and DX 9.3 standards
16 channels
Support data width of 8/16/32 bits
Support linear and IO address modes
DMA channels can be paused during data
transfer if necessary
RTC
2D
- Support BLT and ROP2/3/4, scaling function with

4x4 taps and 32 phases
- Support 90/180/270 degree rotation
- Support mirror/alpha (plane and pixel alpha)/
color key
- Format conversion: ARGB 8888/4444/1555,
RGB565, Mono 1/2/4/8 bpp, Palette 1/2/4/8 bpp
(input only), YUV 444/422/420
- Support command queue
- Real time registers for second, minute, hour, day,

month and year
- Two alarms based on seconds and weeks
- 16 general purpose registers
CCU
- programmable PLLs
MEMORY SUBSYSTEM
Internal
SYSTEM RESOURCES
Timer
- 6 timers: clock source can be switched over

24M/32K for all timers, and external signals can
function as clock source for timer4/5
- 33-bit AVS counter
- 4 watchdogs to generate reset signal or
interrupts
Boot ROM
- Support system boot from 8-bit NAND Flash, SPI
Nor Flash (SPI0) and SD/TF/8-bit eMMC
(SDC0/2)
- Support system code download via USB OTG
(USB0)
DRAM
- Support DDR3/DDR3L/LPDDR2
- Support 32-bit bus width
Page 6
FEATURES
NAND
FLASH
Comply to ONFI 2.3 and toggle 1.0
Support 64-bit ECC per 512 bytes or 1024 bytes
Support 8-bit data bus width
Support 1.8/3.3V signal voltage
Support up to 4 CE and 2 RB
Support system boot from NAND flash
Support SLC/MLC/TLC NAND and EF-NAND
Support SDR/DDR NAND interface
SD/MMC
DRC(dynamic range compression)

RGB2YCbCr
Non-linear 2D sharpening
Advanced contrast enhancement
Advanced spatial (2D) de-noise filter
Zone-based AE/AF/AWB statistics
Anti-flick detection statistics
Histogram statistics
VIDEO ENGINE
Comply to eMMC standard specification v4.5

Comply to SD physical layer specification v3.0
Comply to SDIO card specification v2.0
Support 1/4/8-bit bus width
Support HS/DS/SDR12/SDR25/SDR50 /HS200/
DDR50 bus mode
Support 1.8/3.3V adjustable power for signals
Support eMMC mandatory and alternative boot
operations
Support transmit clock up to100MHz
Support four independent SD/MMC/SDIO
controllers
Support SDSC/SDHC/SDXC/UHS-I/MMC/
RS-MMC Card
Support eMMC/iNand Flash
Support 1GB/2GB/4GB/8GB/16GB/32GB/ 64GB
/128GB SD/MMC card
Support SDIO interrupt detection
Support build-in 64-byte FIFO for buffered read
or write operations
Support descriptor-based internal DMA controller
for efficient scatter and gather operations
Decoder
and encoder can work at the same time

decoding
- Picture size up to 4096x2304
- Decoding speed up to 1920x1080@60fps
- Support multiple video formats: Mpeg1/2, Mpeg4
SP/ASP GMC, H.263 including Sorenson Spark,
H.264 BP/MP/HP, VP6/8, AVS jizun,
JPEG/MJPEG
- Support tiled/YUV/YUV output format
Video Encoding
- H.264 HP: picture size up to 3840x2160
- H.264 HP: speed up to 1920x1080@30fps
- H.264 HP: cyclic intra refresh
- H.264 HP: ROI windows
- JPEG baseline: picture size up to 8192x8192
- Alpha blending
- Thumb generation
- 4x2 scaling ratio: from 1/16 to 64 arbitrary
non-integer ratio
Video
DISPLAY ENGINE
Support
IMAGE SIGNAL PROCESSOR

Support
image mirror flip and rotation

thumb image generation
Support two channels output
Support valid picture size up to 4096x4096
Support speed up to 250M pixel/s
ISP for YCbCr input
- YCbCr gain and offset control
- DRC(dynamic range compression)
- Anti-flick detection statistics
- Histogram statistics
ISP for RAW RGB input
- Black clamp with horizontal/vertical offset
compensation
- Window capture
- Static/dynamic defect pixel correction
- Super lens shading correction
- Super lens flare correction
- Color dependent gain and offset control
- Anisotropic non-linear bayer interpolation with
false color suppression
- Programmable color correction
- Programmable gamma correction
Support
dual display paths

- Each path supports 4 movable and
size-adjustable layers
- Layer size up to 8192x8192 pixels
Ultra-scaling Engine
- 8 taps in horizontal and 4 taps in vertical
- Source image size from 8x4 to 8192x8192
- Destination image size from 8x4 to 8192x8192
Support multiple image input formats
- Mono 1/2/4/8 bpp
- Palette 1/2/4/8 bpp
- 16/24/32 bpp color
- YUV444/420/422/411
Support alpha blending/color
key/gamma/hardware cursor
Support video post processing
- De-interlacing
- Detail enhancement
- Dynamic range control
- Color management
3D input/output format conversion and display
VIDEO OUTPUT
Support
HDMI 1.4 1080p@60fps

LCD interface 1280x800
LVDS/RGB/CPU
Page 7
FEATURES
LRADC
VIDEO INPUT
Support
- Support sample rate up to 250Hz

- Support 6-bit resolution
- Support 0V ~2V voltage input
parallel 12-bit CSI
ANALOG AUDIO INPUT

Support
two audio ADC channels

- 96dBA SNR for ADC recording
- 8KHz~ 48KHz ADC sample rate
Analog low-power loop from line-in/mic-in/
phone-in to headphone/speaker/ earpiece outputs
Accessory button press detection
Four analog audio inputs
- Two differential microphone inputs
- Differential phone-in input
- Stereo line-in input
Support low-noise digital MIC interface
Flexible digital audio process for ADC
- High pass filter and low latency decimation filter
for class voice
- Automatic gain control (AGC)
ANALOG AUDIO OUTPUT

Two-channel
audio DAC
Stereo capless headphone drivers
- Up to 100dBA SNR for DAC playback
- 8KHz~192KHz DAC sample rate
Support analog/digital volume control
Two low-noise analog microphone bias
Dedicated headphone/speaker/earpiece outputs,
single-ended or differential
Support differential phone-out
Support two mixers for different applications
- Output mixer for LINEINL/R, PHONEP/N,
MIC1P/N, MIC2P/N and stereo DAC output
- ADC record mixer for LINEINL/R, PHONEP/N,
MIC1P/N, MIC2P/N, stereo DAC output
Flexible digital audio process for DAC
- Pop suppression control
- Individual high pass filter/De-emphasis filter
- Support EQ equalization
- Soft volume control and soft mute
OTG
- Support High-Speed (HS, 480-Mbps), Full-Speed
(FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps)
in Host mode
- Support High-Speed (HS, 480-Mbps), Full-Speed
(FS, 12-Mbps) in Device mode
- Support up to 10 user-configurable endpoints for
bulk , isochronous, control and interrupt
bi-directional transfers
USB
EHCI/OHCI
- Two EHCI/OHCI-compliant Hosts
Audio Interface
- Comply to industry standard I2S/PCM
specification
- Two sets I2S/PCM interfaces for baseband and
Bluetooth
- Support Master/Slave mode and full-duplex
operation
- Support 8KHz ~192KHz audio sample rate
- Support MCLK output for CODEC chips
- Support standard I2S, left-justified, right-justified,
8/16-bit linear sample, 8-bit u-law and a-law
companded sample
PWM
- 4 PWM outputs
- Support cycle mode and pulse mode
- The pre-scale ranges from 1 to 64
Transport
Stream
Support both SPI and SSI
Support 64 channels PID filter
Support hardware PCR packet detection
Speed up to 150Mbps for both SPI and SSI
interface
CIR
- A flexible receiver for IR remote controller

UART
- Comply to industry-standard 16450/16550 UART

specification
- Support 16-bit programmable baud rate and
dynamic modification
- Support 2-wire serial communication
- Support 4-wire auto data flow communication
- Support 8-wire modem(data carrier equipment,
DCE) or data set
- Support up to 6 UART controllers
SPI
CONNECTIVITY
USB2.0
Digital
- Master/Slave configurable
- Up to 4 independent SPI controllers, SPI0 with
only one CS signal for system boot, and SPI1/2/3
with two CS signals
- Support dual input and dual output operation
TWI
- Up to 5 TWIs compliant with I2C protocol

- Support SCCB protocol
P2WI
(Push-Pull TWI)
- Support speed up to 12MHz
Page 8
FEATURES
One
Wire Interface
- Support both standard One Wire protocol and
simple HDQ protocol
SECURITY SYSTEM
Support AES,
DES, 3DES, SHA-1, MD5

ECB, CBC, CNT modes for
AES/DES/3DES 128-bit, 192-bit and 256-bit key
size for AES
160-bit hardware PRNG with 192-bit seed
Security JTAG
Support
POWER MANAGEMENT
Flexible
PLL clock generator and 32768Hz OSC

clock gate and module reset
Support DVFS for CPU frequency and voltage
adjustment
Support dynamic frequency adjustment for
external DRAM controller
Support standby mode
Flexible
PACKAGE
FBGA
460 balls, 0.8mm ball pitch, 18mm x18mm
Page 9
BLOCK DIAGRAM
BLOCK DIAGRAM
Figure 3-1. A31s Block Diagram
Page 10
PIN DESCRIPTION
PIN DESCRIPTION
4.1. PIN CHARACTERISTICS

Following table describes the A31s pin characteristics.
Notes
1)
2)
3)
4)
5)
6)
7)
Pin Name defines the names of pins. Note that a group of pins with similar meaning may be expressed in the form of [x:0];
Default Function defines the default function of each pin;
Type defines the signal direction: I (Input), O (Output), I/O(Input / Output), A (Analog), P (Power), G (Ground);
Default IO State defines the default IO state of each pin: DIS means disable;
Default Pull Up/Down defines the presence of an internal pull up or pull down resister. Unless otherwise specified, the pin
is default to be floating, and can be configured as pull up or pull down; Note that the NMI and RESET pins require no
additional pull-up resistors;
Buffer Strength defines drive strength of the associated output buffer. It is tested in the condition that VCC= 3.3V,
strength=MAX;
P[A:M] in Table 5-1 stands for GPIO [A:M]. For detailed auxiliary functions of each GPIO, please go to Section 5.2 GPIO
Multiplexing Functions section.
Default
Default
Buffer
Power Supply
4
5
6
IO State Pull Up/Down Strength (mA)
Default
2
Function
Type
SDQ[31:0]
DRAM
I/O
DIS
AA7,AA3,R1,L1,
SDQS[3:0]
DRAM
I/O
DIS
Y8,AB3,R2,L2
SDQSB[3:0]
DRAM
I/O
DIS
AB9,Y4,P4,L4
SDQM[3:0]
DRAM
DIS
V3
SCK
DRAM
DIS
W3
SCKB
DRAM
DIS
Ball#
Pin Name
Y9,Y6,AA8,AA6,AA9,Y7
,AB8,AB6,AA4,AA1,AB5
,AA2,AA5,AB1,Y5,AB2,
T2,N2,P3,P1,R3,N3,U1,
P2,M1,J2,L3,K2,M2,J1,
M3,K3
DRAM
Y3,T5
SCKE[1:0]
DRAM
DIS
V4,W8,Y2,W6,V10,U5,Y
1,V8,W2,V9,V2,W9,T3,
R5,W4,U3
SA[15:0]
DRAM
DIS
V1
SWE
DRAM
DIS
N5
SCAS
DRAM
DIS
L5
SRAS
DRAM
DIS
N4,R4
SCS[1:0]
DRAM
DIS
T4,V5,U2
SBA[2:0]
DRAM
DIS
M5,M4
SODT[1:0]
DRAM
DIS
U4
SRST
DRAM
DIS
K4
SZQ
DRAM
VCC_DRAM
Page 11
PIN DESCRIPTION
Default
2
Function
Type
SVREF
DRAM
P6,R6,T6,T7,U6,U7,U8,
V6,V7,W7,
VCC-DRAM
(10)
DRAM
U9
VDD-DLL
DRAM
F18
PA0
GPIO
I/O
DIS
20
E19
PA1
GPIO
I/O
DIS
20
G18
PA2
GPIO
I/O
DIS
20
F19
PA3
GPIO
I/O
DIS
20
D20
PA4
GPIO
I/O
DIS
20
H18
PA5
GPIO
I/O
DIS
20
J18
PA6
GPIO
I/O
DIS
20
C20
PA7
GPIO
I/O
DIS
20
C21
PA8
GPIO
I/O
DIS
20
C22
PA9
GPIO
I/O
DIS
20
J19
PA10
GPIO
I/O
DIS
20
H19
PA11
GPIO
I/O
DIS
20
G19
PA12
GPIO
I/O
DIS
20
D21
PA13
GPIO
I/O
DIS
20
E20
PA14
GPIO
I/O
DIS
20
Ball#
Pin Name
W5
Default
Default
Buffer
Power Supply
4
5
6
GPIO A
G20
PA15
GPIO
I/O
DIS
20
F20
PA16
GPIO
I/O
DIS
20
E21
PA17
GPIO
I/O
DIS
20
E22
PA18
GPIO
I/O
DIS
20
F21
PA19
GPIO
I/O
DIS
20
F22
PA20
GPIO
I/O
DIS
20
H20
PA21
GPIO
I/O
DIS
20
G21
PA22
GPIO
I/O
DIS
20
H21
PA23
GPIO
I/O
DIS
20
J21
PA24
GPIO
I/O
DIS
20
J20
PA25
GPIO
I/O
DIS
20
H22
PA26
GPIO
I/O
DIS
20
J22
PA27
GPIO
I/O
DIS
20
M17,N17
VCC-PA
POWER
B19
PB0
GPIO
I/O
DIS
20
C19
PB1
GPIO
I/O
DIS
20
A20
PB2
GPIO
I/O
DIS
20
B20
PB3
GPIO
I/O
DIS
20
VCC-PA
GPIO B
A21
PB4
GPIO
I/O
DIS
20
B21
PB5
GPIO
I/O
DIS
20
A22
PB6
GPIO
I/O
DIS
20
VCC-PB
Page 12
PIN DESCRIPTION
Default
2
Function
Type
PB7
GPIO
I/O
DIS
20
D19
VCC-PB
POWER
G2
PC0
GPIO
I/O
DIS
20
H3
PC1
GPIO
I/O
DIS
20
H4
PC2
GPIO
I/O
DIS
20
H5
PC3
GPIO
I/O
DIS
Pull-up
20
F1
PC4
GPIO
I/O
DIS
Pull-up
20
G3
PC5
GPIO
I/O
DIS
20
G4
PC6
GPIO
I/O
DIS
Pull-up
20
G5
PC7
GPIO
I/O
DIS
Pull-up
20
F2
PC8
GPIO
I/O
DIS
20
F3
PC9
GPIO
I/O
DIS
20
E2
PC10
GPIO
I/O
DIS
20
Ball#
Pin Name
BAA
Default
Default
Buffer
Power Supply
4
5
6
GPIO C
D3
PC11
GPIO
I/O
DIS
20
F4
PC12
GPIO
I/O
DIS
20
F5
PC13
GPIO
I/O
DIS
20
E5
PC14
GPIO
I/O
DIS
20
E4
PC15
GPIO
I/O
DIS
20
D4
PC24
GPIO
I/O
DIS
20
H6
PC25
GPIO
I/O
DIS
Pull-up
20
C2
PC26
GPIO
I/O
DIS
Pull-up
20
C3
PC27
GPIO
I/O
DIS
Pull-up
20
E8,F8
VCC-PC
POWER
W18
PD0
GPIO
I/O
DIS
20
V18
PD1
GPIO
I/O
DIS
20
W17
PD2
GPIO
I/O
DIS
20
V17
PD3
GPIO
I/O
DIS
20
W16
PD4
GPIO
I/O
DIS
20
V16
PD5
GPIO
I/O
DIS
20
W15
PD6
GPIO
I/O
DIS
20
V15
PD7
GPIO
I/O
DIS
20
W14
PD8
GPIO
I/O
DIS
20
V14
PD9
GPIO
I/O
DIS
20
Y18
PD10
GPIO
I/O
DIS
20
AA19
PD11
GPIO
I/O
DIS
20
AB18
PD12
GPIO
I/O
DIS
20
AA18
PD13
GPIO
I/O
DIS
20
AB17
PD14
GPIO
I/O
DIS
20
AA17
PD15
GPIO
I/O
DIS
20
VCC-PC
GPIO D
VCC-PD
Page 13
PIN DESCRIPTION
Default
2
Function
Type
PD16
GPIO
I/O
DIS
20
AB15
PD17
GPIO
I/O
DIS
20
AA16
PD18
GPIO
I/O
DIS
20
Y16
PD19
GPIO
I/O
DIS
20
Y15
PD20
GPIO
I/O
DIS
20
Y17
PD21
GPIO
I/O
DIS
20
W13
PD22
GPIO
I/O
DIS
20
V13
PD23
GPIO
I/O
DIS
20
W12
PD24
GPIO
I/O
DIS
20
V12
PD25
GPIO
I/O
DIS
20
W11
PD26
GPIO
I/O
DIS
20
V11
PD27
GPIO
I/O
DIS
20
R16,R17,P16
VCC-PD
POWER
B10
PE0
GPIO
I/O
DIS
20
A11
PE1
GPIO
I/O
DIS
20
C11
PE2
GPIO
I/O
DIS
20
B11
PE3
GPIO
I/O
DIS
20
D12
PE4
GPIO
I/O
DIS
20
E12
PE5
GPIO
I/O
DIS
20
D13
PE6
GPIO
I/O
DIS
20
D14
PE7
GPIO
I/O
DIS
20
A12
PE8
GPIO
I/O
DIS
20
B12
PE9
GPIO
I/O
DIS
20
C12
PE10
GPIO
I/O
DIS
20
B13
PE11
GPIO
I/O
DIS
20
C13
PE12
GPIO
I/O
DIS
20
A14
PE13
GPIO
I/O
DIS
20
B14
PE14
GPIO
I/O
DIS
20
C14
PE15
GPIO
I/O
DIS
20
E13
VCC-PE
POWER
D5
PF0
GPIO
I/O
DIS
20
J3
PF1
GPIO
I/O
DIS
20
J4
PF2
GPIO
I/O
DIS
20
J5
PF3
GPIO
I/O
DIS
20
H1
PF4
GPIO
I/O
DIS
20
H2
PF5
GPIO
I/O
DIS
20
E7
VCC-PF
POWER
A15
PG0
GPIO
I/O
DIS
20
Ball#
Pin Name
AA15
Default
Default
Buffer
Power Supply
4
5
6
GPIO E
VCC-PE
GPIO F
GPIO G
VCC-PF
VCC-PG
Page 14
PIN DESCRIPTION
Default
2
Function
Type
PG1
GPIO
I/O
DIS
20
C15
PG2
GPIO
I/O
DIS
20
B16
PG3
GPIO
I/O
DIS
20
C16
PG4
GPIO
I/O
DIS
20
A17
PG5
GPIO
I/O
DIS
20
D15
PG6
GPIO
I/O
DIS
20
E15
PG7
GPIO
I/O
DIS
20
D16
PG8
GPIO
I/O
DIS
20
E16
PG9
GPIO
I/O
DIS
20
B17
PG10
GPIO
I/O
DIS
20
C17
PG11
GPIO
I/O
DIS
20
D17
PG12
GPIO
I/O
DIS
20
E17
PG13
GPIO
I/O
DIS
20
A18
PG14
GPIO
I/O
DIS
20
B18
PG15
GPIO
I/O
DIS
20
C18
PG16
GPIO
I/O
DIS
20
D18
PG17
GPIO
I/O
DIS
20
E18
PG18
GPIO
I/O
DIS
20
E14
VCC-PG
POWER
C5
PH9
GPIO
I/O
DIS
20
B5
PH10
GPIO
I/O
DIS
20
A5
PH11
GPIO
I/O
DIS
20
E6
PH12
GPIO
I/O
DIS
20
D6
PH13
GPIO
I/O
DIS
20
C6
PH14
GPIO
I/O
DIS
20
B6
PH15
GPIO
I/O
DIS
20
A6
PH16
GPIO
I/O
DIS
20
B7
PH17
GPIO
I/O
DIS
20
C7
PH18
GPIO
I/O
DIS
20
D7
PH19
GPIO
I/O
DIS
20
Ball#
Pin Name
B15
Default
Default
Buffer
Power Supply
4
5
6
GPIO H
A8
PH20
GPIO
I/O
DIS
20
B8
PH21
GPIO
I/O
DIS
20
C8
PH22
GPIO
I/O
DIS
20
E9
PH23
GPIO
I/O
DIS
20
A9
PH24
GPIO
I/O
DIS
20
B9
PH25
GPIO
I/O
DIS
20
C9
PH26
GPIO
I/O
DIS
20
D8
PH27
GPIO
I/O
DIS
20
D9
PH28
GPIO
I/O
DIS
20
F9,F10
VCC-PH
POWER
VCC-PH
Page 15
PIN DESCRIPTION
Default
2
Function
Type
PL0
GPIO
I/O
DIS
Pull-up
20
AB20
PL1
GPIO
I/O
DIS
Pull-up
20
W21
PL2
GPIO
I/O
DIS
20
U20
PL3
GPIO
I/O
DIS
20
Y20
PL4
GPIO
I/O
DIS
20
U19
PL5
GPIO
I/O
DIS
20
Y19
PL6
GPIO
I/O
DIS
20
W20
PL7
GPIO
I/O
DIS
20
V20
PL8
GPIO
I/O
DIS
20
R19
PM0
GPIO
I/O
DIS
20
R18
PM1
GPIO
I/O
DIS
20
R20
PM2
GPIO
I/O
DIS
20
T18
PM3
GPIO
I/O
DIS
20
R21
PM4
GPIO
I/O
DIS
20
T20
PM5
GPIO
I/O
DIS
20
T19
PM6
GPIO
I/O
DIS
20
T21
PM7
GPIO
I/O
DIS
20
U18
VCC-PM
POWER
UBOOT
Pull-up
Ball#
Pin Name
U21
Default
Default
Buffer
Power Supply
4
5
6
GPIO L
GPIO M
VCC-RTC
VCC-PM
System Control
E10
VCC_PH
E11,D11
JTAG_SEL
Pull-up
VCC_PH
G9,G10
BOOT_SEL
Pull-up
VCC_PH
W19
NMI
I/O
VCC_RTC
U22
RESET
VCC_RTC
AA12
HTX0P
AB12
HTX0N
AA13
HTX1P
Y12
HTX1N
AA14
HTX2P
HDMI
Y14
HTX2N
AB11
HTXCP
AA11
HTXCN
VCC-HDMI
U17
VCC-HDMI
AB14
HSCL
Y13
HSDA
Y11
HHPD
Y21
DM0
USB
VCC-USB
Page 16
PIN DESCRIPTION
Default
2
Function
Type
DP0
AA21
DM1
AA22
DP1
T17
VCC-USB
AB21
DM2
AB22
DP2
P18
PHOUTN
P19
PHOUTP
L21
PHINP
L22
PHINN
P20
HBIAS
N20
MBIAS
M22
MIC2N
M21
MIC2P
M20
MIC1N
L20
MIC1P
K19
VRA1
K20
VRA2
L18
AVCC
K18
VRP
P21
LINEOUTR
P22
LINEOUTL
N19
LINEINR
M19
LINEINL
N16
AGND
K21
HPOUTR
L19
HPOUTL
M18
HPCOMFB
N18
HPCOM
N21
HPBP
P17
VCC-HP
R22
LRADC0
AA10
X24MI
Y10
X24MO
AA20
VIO-RTC
V19
VCC-RTC
V22
X32KI
Ball#
Pin Name
Y22
Default
Default
Buffer
Power Supply
4
5
6
Audio Codec
AVCC
LRADC
AVCC
RTC
VCC-RTC
Clock
VCC-PLL
Page 17
PIN DESCRIPTION
Default
2
Function
Type
X32KO
L16,L17
VDD-CPUS
F11,F12,F13,F14,F15,F
16,G11,G12,G13,G14,G
15,G16,G17,H12,H13,H
14,H15,H16,H17,J16,J1
7,K16,K17
VDD-CPU
(23)
F17
CPU-VDDFB
J6,J7,K5,K6,K7,L6,L7,M
6,M7,N6,N7,P5
T12,T13,T14,T15,T16,U
10,U11,U12,U13,U14,U
15,U16
W10,G8,H8,H9,H10,H1
1,J8,J9,J10,J11,J12,J13
,J14,J15,K8,K9,K10,K11
,K12,K13,K14,K15,L8,L
9,L10,L11,L12,L13,L14,
L15,M8,M9,M10,M11,M
12,M13,M14,M15,M16,
N8,N9,N10,N11,N12,N1
3,N14,N15,P7,P8,P9,P1
0,P11,P12,P13,P14,P15
,R7,R8,R9,R10,R11,R1
2,R13,R14,R15,T8,T9,T
10,T11
VDD-GPU
(12)
VDD-SYS
(12)
GND(69)
NC
Ball#
Pin Name
V21
Default
Default
Buffer
Power Supply
4
5
6
Power
Others
A1,A2,A3,B1,B2,B3,B4,
C1,C4,D2,E1,E3,F6,F7,
G6,G7,H7,C10.D10
Table 5-1 Pin Characteristics
4.2. GPIO MULTIPLEXING FUNCTIONS

The following table provides a description of the A31s GPIO multiplexing functions.
Pin
Name
Default
Function
IO
Type
Default
IO State
PA0
I/O
DIS
PA1
I/O
DIS
PA2
I/O
DIS
PA3
I/O
DIS
PA4
I/O
DIS
PA5
I/O
DIS
PA6
I/O
DIS
PA7
I/O
DIS
PA8
I/O
DIS
GPIO
PA9
I/O
PA10
I/O
PA11
I/O
DIS
PA12
I/O
DIS
PA13
I/O
DIS
DIS
DIS
Default
Pull-up/
down
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Function2
Function 3
Function 4
Function 5
UART1_DTR
UART1_DSR
UART1_DCD
UART1_RING
UART1_TX
UART1_RX
UART1_RTS
UART1_CTS
ECLK_IN0
SDC3_CMD
SDC2_CMD
SDC3_CLK
SDC2_CLK
SDC3_D0
SDC2_D0
SDC3_D1
SDC2_D1
SDC3_D2
SDC2_D2
Function 6
PA_EINT0
PA_EINT1
PA_EINT2
PA_EINT3
PA_EINT4
PA_EINT5
PA_EINT6
PA_EINT7
PA_EINT8
PA_EINT9
PA_EINT10
PA_EINT11
PA_EINT12
PA_EINT13
Page 18
PIN DESCRIPTION
Pin
Name
Default
Function
IO
Type
Default
IO State
PA14
I/O
DIS
PA15
I/O
DIS
PA16
I/O
DIS
PA17
I/O
DIS
PA18
I/O
DIS
PA19
I/O
DIS
PA20
I/O
DIS
PA21
I/O
DIS
PA22
I/O
DIS
PA23
I/O
DIS
PA24
I/O
DIS
PA25
I/O
DIS
PA26
I/O
DIS
PA27
I/O
DIS
PB0
I/O
PB1
I/O
PB2
I/O
PB3
I/O
GPIO
PB4
I/O
PB5
I/O
PB6
I/O
PB7
I/O
PC0
I/O
PC1
I/O
PC2
I/O
PC3
I/O
PC4
I/O
PC5
I/O
PC6
I/O
PC7
I/O
PC8
I/O
PC9
GPIO
I/O
PC10
I/O
PC11
I/O
PC12
I/O
PC13
I/O
PC14
I/O
PC15
I/O
PC24
I/O
PC25
I/O
PC26
I/O
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Default
Pull-up/
down
Function2
Function 3
Function 4
Function 5
SDC3_D3
SDC2_D3
CLKA_OUT
DMIC_CLK
DMIC_DIN
CLKB_OUT
PWM3_P
PWM3_N
SPI3_CLK
SPI3_MOSI
SPI3_MISO
CLKC_OUT
ECLK_IN1
I2S0_MCLK
UART3_CTS
I2S0_BCLK
I2S0_LRCK
I2S0_DO0
I2S0_DO1
UART3_RTS
I2S0_DO2
UART3_TX
I2S0_DO3
UART3_RX
I2S0_DI
NAND_WE
Function 6
PA_EINT14
PA_EINT15
PA_EINT16
PA_EINT17
PA_EINT18
PA_EINT19
PA_EINT20
PA_EINT21
PA_EINT22
PA_EINT23
PA_EINT24
PA_EINT25
PA_EINT26
PA_EINT27
PB_EINT0
PB_EINT1
PB_EINT2
PB_EINT3
PB_EINT4
PB_EINT5
PB_EINT6
PB_EINT7
SPI0_MOSI
NAND_ALE
SPI0_MISO
NAND_CLE
SPI0_CLK
Pull-up
NAND_CE1
Pull-up
NAND_CE0
NAND_RE
Pull-up
NAND_RB0
SDC2_CMD
SDC3_CMD
Pull-up
NAND_RB1
SDC2_CLK
SDC3_CLK
NAND_DQ0
SDC2_D0
SDC3_D0
NAND_DQ1
SDC2_D1
SDC3_D1
NAND_DQ2
SDC2_D2
SDC3_D2
NAND_DQ3
SDC2_D3
SDC3_D3
NAND_DQ4
SDC2_D4
SDC3_D4
NAND_DQ5
SDC2_D5
SDC3_D5
NAND_DQ6
SDC2_D6
SDC3_D6
NAND_DQ7
SDC2_D7
SDC3_D7
NAND_DQS
SDC2_RST
SDC3_RST
Pull-up
NAND_CE2
Pull-up
NAND_CE3
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
SPI3_CS0
SPI3_CS1
TWI3-SCK
TWI3-SDA
-
Page 19
PIN DESCRIPTION
Pin
Name
Default
Function
IO
Type
PC27
I/O
PD0
I/O
PD1
I/O
PD2
I/O
PD3
I/O
PD4
I/O
PD5
I/O
PD6
I/O
PD7
I/O
PD8
I/O
PD9
I/O
PD10
I/O
PD11
I/O
PD12
I/O
PD13
I/O
GPIO
PD14
I/O
PD15
I/O
PD16
I/O
PD17
I/O
PD18
I/O
PD19
I/O
PD20
I/O
PD21
I/O
PD22
I/O
PD23
I/O
PD24
I/O
PD25
I/O
PD26
I/O
PD27
I/O
PE0
I/O
PE1
I/O
PE2
I/O
PE3
I/O
PE4
I/O
PE5
I/O
GPIO
PE6
I/O
PE7
I/O
PE8
I/O
PE9
I/O
PE10
I/O
PE11
I/O
Default
IO State
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Default
Pull-up/
down
Function2
Function 3
Function 4
Function 5
Function 6
Pull-up
SPI0_CS0
LCD_D0
LVDS_VP0
LCD_D1
LVDS_VN0
LCD_D2
LVDS_VP1
LCD_D3
LVDS_VN1
LCD_D4
LVDS_VP2
LCD_D5
LVDS_VN2
LCD_D6
LVDS_VPC
LCD_D7
LVDS_VNC
LCD_D8
LVDS_VP3
LCD_D9
LVDS_VN3
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_D18
LCD_D19
LCD_D20
LCD_D21
LCD_D22
LCD_D23
LCD_CLK
LCD_DE
LCD_HSYNC
LCD_VSYNC
CSI_PCLK
TS_CLK
PE_EINT0
CSI_MCLK
TS_ERR
PE_EINT1
CSI_HSYNC
TS_SYNC
PE_EINT2
CSI_VSYNC
TS_DVLD
PE_EINT3
CSI_D0
UART5_TX
PE_EINT4
CSI_D1
UART5_RX
PE_EINT5
CSI_D2
UART5_RTS
PE_EINT6
CSI_D3
UART5_CTS
PE_EINT7
CSI_D4
TS_D0
PE_EINT8
CSI_D5
TS_D1
PE_EINT9
CSI_D6
TS_D2
PE_EINT10
CSI_D7
TS_D3
PE_EINT11
Page 20
PIN DESCRIPTION
Pin
Name
Default
Function
IO
Type
PE12
I/O
PE13
I/O
PE14
I/O
PE15
I/O
PF0
I/O
PF1
I/O
PF2
I/O
GPIO
PF3
I/O
PF4
I/O
PF5
I/O
PG0
I/O
PG1
I/O
PG2
I/O
PG3
I/O
PG4
I/O
PG5
I/O
PG6
I/O
PG7
I/O
PG8
I/O
PG9
I/O
PG10
I/O
PG11
I/O
PG12
I/O
PG13
I/O
PG14
I/O
PG15
GPIO
I/O
PG16
I/O
PG17
I/O
PG18
I/O
PH9
I/O
PH10
I/O
PH11
I/O
PH12
I/O
PH13
I/O
PH14
I/O
PH15
I/O
PH16
I/O
PH17
I/O
PH18
I/O
PH19
I/O
PH20
I/O
Default
IO State
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Default
Pull-up/
down
Function2
Function 3
Function 4
Function 5
Function 6
CSI_D8
TS_D4
PE_EINT12
CSI_D9
TS_D5
PE_EINT13
CSI_D10
TS_D6
PE_EINT14
CSI_D11
TS_D7
PE_EINT15
SDC0_D1
JTAG_MS1
SDC0_D0
JTAG_DI1
SDC0_CLK
UART0_TX
SDC0_CMD
JTAG_DO1
SDC0_D3
UART0_RX
SDC0_D2
JTAG_CK1
SDC1_CLK
PG_EINT0
SDC1_CMD
PG_EINT1
SDC1_D0
PG_EINT2
SDC1_D1
PG_EINT3
SDC1_D2
PG_EINT4
SDC1_D3
PG_EINT5
UART2_TX
PG_EINT6
UART2_RX
PG_EINT7
UART2_RTS
PG_EINT8
UART2_CTS
PG_EINT9
TWI3_SCK
PG_EINT10
TWI3_SDA
PG_EINT11
SPI1_CS1
I2S1_MCLK
PG_EINT12
SPI1_CS0
I2S1_BCLK
PG_EINT13
SPI1_CLK
I2S1_LRCK
PG_EINT14
SPI1_MOSI
I2S1_DIN
PG_EINT15
SPI1_MISO
I2S1_DOUT
PG_EINT16
UART4_TX
PG_EINT17
UART4_RX
PG_EINT18
SPI2_CS0
JTAG_MS0
PWM1_P
SPI2_CLK
JTAG_CK0
PWM1_N
SPI2_MOSI
JTAG_DO0
PWM2_P
SPI2_MISO
JTAG_DI0
PWM2_N
PWM0
TWI0_SCK
TWI0_SDA
TWI1_SCK
TWI1_SDA
TWI2_SCK
TWI2_SDA
UART0_TX
Page 21
PIN DESCRIPTION
Pin
Name
Default
Function
IO
Type
PH21
I/O
PH22
I/O
PH23
I/O
PH24
I/O
PH25
I/O
PH26
I/O
PH27
I/O
PH28
I/O
PL0
I/O
PL1
I/O
PL2
I/O
PL3
I/O
GPIO
PL4
I/O
PL5
I/O
PL6
I/O
PL7
I/O
PL8
I/O
PM0
I/O
PM1
I/O
PM2
I/O
PM3
I/O
GPIO
PM4
I/O
PM5
I/O
PM6
I/O
PM7
I/O
Default
IO State
Default
Pull-up/
down
Function2
Function 3
Function 4
Function 5
Function 6
UART0_RX
Pull-up
S_TWI_SCK
S_P2WI_SCK
Pull-up
S_TWI_SDA
S_P2WI_SDA
S_UART_TX
S_UART_RX
S_IR_RX
S_PL_EINT0
S_JTAG_MS
S_PL_EINT1
S_JTAG_CK
S_PL_EINT2
S_JTAG_DO
S_PL_EINT3
S_JTAG_DI
S_PM_EINT0
S_PM_EINT1
S_PM_EINT2
1WIRE
S_PM_EINT3
S_PM_EINT4
S_PM_EINT5
S_PM_EINT6
S_PM_EINT7
RTC_CLKO
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Table 5-2 Multiplexing Functions
4.3. DETAILED PIN/SIGNAL DESCRIPTION
Following table describes A31s pins.

Pin/Signal Name
Description
Type
DRAM
SDQ[31:0]
DRAM DQ[31:0]
I/O
SDQS[3:0]
DRAM Data Strobe DQS[3:0]
I/O
SDQSB[3:0]
DRAM DQSB[3:0]
I/O
SDQM[3:0]
DRAM DQ Mask [3:0]
SCK
DRAM Clock
SCKB
DRAM CKB
SCKE[1:0]
DRAM Clock Enable [1:0]
SA[15:0]
DRAM data Address [15:0]
Page 22
PIN DESCRIPTION
Pin/Signal Name
Description
Type
SWE
DRAM Write Enable
SCAS
DRAM Column Address Strobe
SRAS
DRAM Row Address Strobe
SCS[1:0]
DRAM Chip Select [1:0]
SBA[2:0]
DRAM Bank Address [2:0]
SODT[1:0]
DRAM ODT Control [1:0]
SRST
DRAM Reset
SZQ
DRAM ZQ Calibration
SVREF
DRAM Reference Input
VCC-DRAM
DRAM Power Supply
VDD-DLL
DLL Power Supply
GPIO
PA[27:0]
GPIO A Bit [27:0]
I/O
VCC-PA
GPIO A Power Supply
PB[7:0]
GPIO B Bit [7:0]
VCC-PB
GPIO B Power Supply
PC[27:0]
GPIO C Bit [27:0]
VCC-PC
GPIO C Power Supply
PD[27:0]
GPIO D Bit [27:0]
VCC-PD
GPIO D Power Supply
PE[15:0]
GPIO E Bit [16:0]
VCC-PE
GPIO E Power Supply
PF[5:0]
GPIO F Bit [5:0]
VCC-PF
GPIO F Power Supply
PG[18:0]
GPIO G Bit [18:0]
VCC-PG
GPIO G Power Supply
PH[30:0]
GPIO H Bit[30:0]
VCC-PH
GPIO H Power Supply
PL[8:0]
GPIO L Bit [8:0]
I/O
PM[7:0]
GPIO M Bit [7:0]
I/O
VCC-PM
GPIO M Power Supply
UBOOT
UBOOT
JTAG_SEL
JTAG Mode Select
BOOT_SEL
BOOT Mode Select
NMI
Non-Maskable Interrupt
RESET
RESET Signal
HTX0P
TMSD Data 0 Positive
HTX0N
TMSD Data 0 Negative
HTX1P
HTX1N
P
I/O
P
I/O
P
I/O
P
I/O
P
I/O
P
I/O
P
I/O
P
System Control
I/O
HDMI
Page 23
PIN DESCRIPTION
Pin/Signal Name
Description
Type
HTX2P
HTX2N
HTXCP
TMSD Clock Positive
HTXCN
TMSD Clock Negative
VCC-HDMI
HDMI Power Supply
HSCL
HDMI DDC Clock
HSDA
HDMI DDC Data
HHPD
HDMI Hot Plug Detection signal
USB_DM0
USB DM0 Signal
USB_DP0
USB DP0 Signal
USB_DM1
USB DM1 Signal
USB_DP1
USB DP1 Signal
VCC-USB
USB Power Supply
USB_DM2
USB DM2 Signal
USB_DP2
USB DP2 Signal
PHOUTN
Phone Negative Output
PHOUTP
Phone Positive Output
PHINP
Phone Positive Input
PHINN
Phone Negative Input
HBIAS
Headphone Microphone Bias
MBIAS
Master Analog Microphone Bias
MIC2N
MIC Negative Input 2
MIC2P
MIC Positive Input 2
MIC1N
MIC Negative Input 1
MIC1P
MIC Positive Input 1
VRA1
Reference (1.5 V)
VRA2
Reference (1.5 V)
AVCC
Analog Power Supply
VRP
Reference (3.0 V)
LINEOUTR
LINE-OUT Right Channel Output
LINEOUTL
LINE-OUT Left Channel Output
LINEINR
LINE-IN Right Channel Input
LINEINL
LINE-IN Left Channel Input
AGND
Analog Ground
HPOUTR
Headphone Right Channel Output
HPCOMFB
Headphone Common Reference Feedback
HPCOM
Headphone Common Reference
HPBP
Headphone Bypass Output
VCC-HP
Headphone Power Supply
HPOUTL
Headphone Left Channel Output
USB
Audio Codec
Page 24
PIN DESCRIPTION
Pin/Signal Name
Description
Type
LRADC
LRADC0
LRADC Input0
RTC-VIO
RTC Power
VCC-RTC
RTC Power Supply
X24MI
Clock Input Of 24MHz Crystal
X24MO
Clock Output Of 24MHz Crystal
X32KI
Clock Input Of 32768Hz Crystal
X32KO
Clock Output Of 32768Hz Crystal
Clock
SD (x=[3:0])
SDCx_CMD
SDx/MMCx/SDIOx Command Signal
I/O
SDCx_CLK
SDx/MMCx/SDIOx Clock
I/O
SDC0_D[3:0]
SD0/MMC0/SDIO0 Data [3:0]
I/O
SDC1_D[3:0]
I/O
SDC2_D[7:0]
I/O
SDC3_D[7:0]
I/O
SDC2_RST
SD2/MMC2/SDIO2 Reset Signal
I/O
SDC3_RST
SD3/MMC3/SDIO3 Reset Signal
I/O
NAND_DQ[7:0]
NAND Flash Data Bit [7:0]
I/O
NAND_DQS
NADN Flash Data Strobe
I/O
NAND_WE
NAND Flash Write Enable
I/O
NAND_RE
NAND Flash chip Read Enable
I/O
NAND_ALE
NAND Flash Address Latch Enable
I/O
NAND_CLE
NAND Command Latch Enable
I/O
NAND_CE[3:0]
NAND Flash Chip Select [3:0]
I/O
NAND_RB[1:0]
NAND Flash Ready/Busy Bit
I/O
S_JTAG_MS
N/A
I/O
S_JTAG_CK
N/A
I/O
S_JTAG_DO
N/A
I/O
S_JTAG_DI
N/A
I/O
JTAG_MS[1:0]
N/A
I/O
JTAG_CK[1:0]
N/A
I/O
JTAG_DO[1:0]
N/A
I/O
JTAG_DI[1:0]
N/A
I/O
PA_EINT[27:0]
GPIO A Interrupt
I/O
PB_EINT[7:0]
GPIO B Interrupt
I/O
PE_EINT[15:0]
GPIO E Interrupt
I/O
S_PL_EINT[3:0]
GPIO L Interrupt
I/O
S_PM_EINT[7:0]
GPIO M Interrupt
I/O
NAND
JTAG
Interrupt
Page 25
PIN DESCRIPTION
Pin/Signal Name
Description
Type
PWM (x=[3:1])
PWMx_P
PWM Output Positive
I/O
PWMx_N
PWM Output Negative
I/O
PWM0
PWM 0
I/O
IR Data Receive
I/O
LCD_D[23:0]
LCD Data Bit [23:0]
LCD_CLK
LCD Clock signal
LCD_DE
LCD Data Enable
LCD_HSYNC
LCD Horizontal SYNC
LCD_VSYNC
LCD Vertical SYNC
LVDS_VP[3:0]
LVDS Data Positive Signal Output[3:0]
LVDS_VN[3:0]
LVDS Data Negative Signal Output[3:0]
LVDS_VPC
LVDS Clock Positive Signal Output
LVDS_VNC
LVDS Clock Negative Signal Output
I2Sx_MCLK
I2S Master Clock (system clock)
I2Sx_BCLK
I2S Bit Clock
I/O
I2Sx_LRCK
I2S Left/Right Channel Select Clock
I/O
I2S1_DIN
I2S1 Data Input
I2S1_DOUT
I2S1 Data Output
I2S0_DO[3:0]
I2S0 Data Output
I2S0_DI
I2S0 Data Input
CSI_PCLK
CSI Pixel Clock
CSI_MCLK
CSI Master Clock
CSI_HSYNC
CSI Horizontal SYNC
CSI_VSYNC
CSI Vertical SYNC
CSI_D[11:0]
CSI Data bit [11:0]
IR
S_IR_RX
LCD
LVDS
I2S (x=[1:0])
CSI
TS
TS_CLK
Transport Stream Clock
I/O
TS_ERR
Transport Stream Error Indicate
I/O
TS_SYNC
Transport Stream SYNC
I/O
TS_DVLD
Transport Stream Valid Signal
I/O
TS_D[7:0]
Transport Stream Data
I/O
SPI0_CS0
SPI0 Chip Select signal 0
SPI1_CS[1:0]
SPI1 Chip Select signal[1:0]
I/O
I/O
SPI2_CS0
SPI2 Chip Select signal 0
SPI3_CS[1:0]
SPI3 Chip Select signal [1:0]
SPI (x=[3:0])
I/O
I/O
Page 26
PIN DESCRIPTION
Pin/Signal Name
Description
Type
SPIx_CLK
SPI Clock signal
I/O
SPIx_MOSI
SPI Master data Out, Slave data In
I/O
SPIx_MISO
SPI Master data In, Slave data Out
I/O
UART1_DTR
UART Data Terminal Ready
UART1_DSR
UART Data Set Ready
UART1_DCD
UART Data Carrier Detect
UART1_RING
UART RING indicator
UARTx_CTS
UART Data Clear To Send
UARTx_RTS
UART Data Request To Send
UARTx_TX[5:0]
UART Data Transmit
UARTx_RX[5:0]
UART Data Receive
S_UART_TX
UART Data Transmit
S_UART_RX
UART Data Receive
UART (x=[5:0])
TWI (x=[3:0])
TWIx_SCK
TWI Serial Clock Signal
I/O
TWIx_SDA
TWI Serial Data Signal
I/O
S_TWI_SCK
TWI Serial Clock Signal
I/O
S_TWI_SDA
TWI Serial Data Signal
I/O
S_P2WI_SCK
P2WI Serial Clock Signal
I/O
S_P2WI_SDA
P2WI Serial Data Signal
I/O
One WIRE signal
I/O
CLKA_OUT
CLOCK OUT A
I/O
CLKB_OUT
CLOCK OUT B
I/O
CLKC_OUT
CLOCK OUT C
I/O
CK32KO
32K Crystal Clock Output
I/O
RTC_CLKO
RTC Clock Output

Table 5-3 Detailed Pin Description
I/O
One Wire
1WIRE
Clock
4.4. POWER/GND SIGNAL DESCRIPTION

Note
1)
VRP/VRA1/VRA2 are output type, and are not for third party development use.
Signal Name
Description
Ball#
HDMI
VCC-HDMI
HDMI Power Supply
(2.7V-3.3V)
U17
USB Power
VCC-USB
USB Power Supply
(2.7V-3.3V)
T17
Page 27
PIN DESCRIPTION
Signal Name
Description
Ball#
IO Power
VCC-PA
Power Supply for GPIO A (1.8V-3.3V)
VCC-PB
Power Supply for GPIO B
(1.8V-3.3V)
M17,N17
D19
VCC-PC
Power Supply for GPIO C
(1.8V-3.3V)
E8,F8
VCC-PD
Power Supply for GPIO D
(2.8V-3.3V)
P16,R16,R17
VCC-PE
Power Supply for GPIO E
(1.8V-3.3V)
E13
VCC-PF
Power Supply for GPIO F
(1.8V-3.3V)
E7
VCC-PG
Power Supply for GPIO G
(1.8V-3.3V)
E14
VCC-PH
Power Supply for GPIO H
(1.8V-3.3V)
F9,F10
VCC-PM
Power Supply for GPIO M (1.8V-3.3V)
U18
RTC Power Supply (3.0V)
V19
RTC
VCC_RTC
DRAM Power
VCC-DRAM
DRAM Power Supply (1.2V-2.5V)
VDD-DLL
DLL Power Supply
P6,R6,T6,T7,U6,U7,U8,V6,V7,W7
(1.1V)
U9
Audio Codec
AVCC
Analog Power Supply (3.0V)
L18
AGND
Analog Ground
N16
VRP
VRP=3.0V, output;
K18
VRA1
VRA1=1.5V,output;
K19
VRA2
VRA2=1.5V,output;
K20
VCC-HP
Headphone Power Supply (3.3V)
P17
CPU&GPU
VDD-CPU
CPU Power Supply (1.1V)
VDD-GPU
GPU Power Supply
(1.1V)
F11,F12,F13,F14,F15,F16,G11,G12
,G13,G14,G15,G16,G17,H12,H13,H
14,H15,H16,H17,J16,J17,K16,K17
J6,J7,K5,K6,K7,L6,L7,M6,M7,N6,N7
,P5
System
VDD-SYS
System Power Supply
(1.1V)
VDD-CPUS
System Power Supply
(1.1V)
T12,T13,T14,T15,T16,U10,U11,U12
,U13,U14,U15,U16
L16,L17
Ground
GND
Ground
W10,G8,H8,H9,H10,H11,J8,J9,J10,
J11,J12,J13,J14,J15,K8,K9,K10,K1
1,K12,K13,K14,K15,L8,L9,L10,L11,
L12,L13,L14,L15,M8,M9,M10,M11,
M12,M13,M14,M15,M16,N8,N9,N10
,N11,N12,N13,N14,N15,P7,P8,P9,P
10,P11,P12,P13,P14,P15,R7,R8,R9
,R10,R11,R12,R13,R14,R15,T8,T9,
T10,T11
Table 5-4 A31s Power/Ground Signal Description
Page 28
ELECTRICAL CHARACTERISTICS
5.1. ABSOLUTE MAXIMUM RATINGS

Prolonged exposure to absolute maximum ratings (as shown in Table 5-1) may reduce device reliability.
Functional operation at these maximum ratings is not implied.
Symbol
II/O
Parameter
Min
In/Out current for input and output

HBM(human body mode)
Max
Unit
mA
VESD
N/A
N/A
N/A
VESD
ESD stress voltage
VCC
Power supply for I/O
3.6
VDD
Power supply for Internal Digital Logic
1.32
CDM(charged device mode)
AVCC
Power supply for Analog Part
3.0
3.0
VCC-DRAM
Power supply for DRAM Part
1.2
2.5
3.3
VCC-USB
Power supply for USB PHY
VDD-DLL
Power supply for DLL
1.1
1.1
VDD-CPU
Power supply for CPU
0.7
1.32
VDD-GPU
Power supply for GPU
0.7
1.32
125
Tg
Storage temperature
Table 5-1
Absolute Maximum Ratings
5.2. RECOMMENDED OPERATING CONDITIONS

All A31s modules are strongly recommended to be used under the Operating Conditions given in following
Table 5-2.
Symbol
Ta
Parameter
Ambient operating temperature
Min
Typ
Max
Unit
(Commercial)
-20
+70
(Extended)
N/A
N/A
N/A
Power supply for the IO
3.3
Power supply For analog part
3.0
Power supply For DRAMC
1.2
1.5/1.8
2.5
VCC-USB
Power supply For USB PHY
2.8
3.3
3.3
VCC
AVCC
VCC-DRAM
VDD-DLL
Power supply For DLL
1.1
1.1
1.1
VCC-RTC
Power supply For RTCLDO/LOSC/RCOSC
2.8
3.0
3.3
VDD-SYS
Power supply for VDD_SYS
0.7
1.1
1.32
VDD-CPU
Power supply for CPU
0.7
1.1
1.32
VDD-GPU
Power supply for GPU
0.7
1.1
1.32
Page 29
VCC-HDMI
GND
Power supply for HDMI
2.8
3.0
3.3
Min
Typ
Max
Unit
VCC = 3.3V
2.1
3.3
3.6
VCC = 1.8V
1.2
1.8
3.6
VCC = 3.3V
-0.3
0.7
Ground
0
Recommended Operating Conditions
Table 5-2
5.3. DC ELECTRICAL CHARACTERISTICS

Table 5-3 summarizes the DC electrical characteristics of A31s.
Symbo
l
Parameter
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
IIH
High-Level Input Current
IIL
Low-Level Input Current
Test Conditions
VOH
High-Level Output Voltage
VOL
Low-Level Output Voltage
IOZ
Tri-State Output Leakage Current
CIN
COUT
Input Capacitance
Output Capacitance
VCC = 1.8V
-0.3
0.6
VCC = 3.3V, VI = 3.3V
TBD
TBD
TBD
uA
VCC = 1.8V, VI = 1.8V
TBD
TBD
TBD
uA
VCC = 3.3V, VI = 0V
TBD
TBD
TBD
uA
VCC = 1.8V, VI = 0V
TBD
TBD
TBD
uA
VCC = 3.3V
2.7
3.3
N/A
VCC = 1.8V
1.5
1.8
N/A
VCC = 3.3V
N/A
0.4
VCC = 1.8V
N/A
0.3
VCC = 3.3V
TBD
TBD
TBD
uA
VCC = 1.8V
TBD
TBD
TBD
uA
N/A
N/A
pF
N/A
DC Electrical Characteristics
N/A
pF
Table 5-3
5.4. OSCILLATOR ELECTRICAL CHARACTERISTICS

The A31s clock control module includes 11PLLs, a main oscillator, an on-chip RC oscillator of 466.9KHz
~867.1KHz, and a 32768Hz low power oscillator.
The 24.000MHz frequency is used to generate the main source clock for PLL and the main digital blocks, and
the 32768Hz oscillator is used only to provide a low power accurate reference for RTC.
24MHz Oscillator Characteristics

Table 5-4 lists the 24MHz crystal specifications.
Symbol
1/(tCPMAIN)
tST
Parameter
Crystal Oscillator Frequency Range
Startup Time
Frequency Tolerance at 25 C
Oscillation Mode
Min
Typ
Max
Unit
24.000
MHz
+40
ppm
-40
Fundamental
ms
Page 30
-50
+50
ppm
Drive level
50
uW
Equivalent Load capacitance
pF
Internal Load capacitance(CL1=CL2)
pF
Series Resistance(ESR)
Duty Cycle
30
50
70
Motional capacitance
pF
Shunt capacitance
pF
Maximum change over temperature range

PON
CL
CL1,CL2
RS
CM
CSHUT
RBIAS
Internal bias resistor

Table 5-4 24MHz Oscillator Characteristics
32768Hz Oscillator Characteristics

The 32768Hz crystal is connected between the LOSCI (amplifier input) and LOSCO (amplifier output). Table
5-5 lists the 32768Hz crystal specifications.
Symbol
1/(tCPMAIN)
tST
Parameter
Min
Crystal Oscillator Frequency Range

Startup Time
Frequency Tolerance at 25 C
-40
Unit
kHz
ms
+40
ppm
Fundamental
-50
+50
ppm
Drive level
50
uW
Equivalent Load capacitance
pF
Maximum change over temperature range

CL
Max
32.768
Oscillation Mode
PON
Typ
Internal Load capacitance(CL1=CL2)
pF
Series Resistance(ESR)
Duty Cycle
30
50
70
Motional capacitance
pF
CSHUT
Shunt capacitance
pF
RBIAS
Internal bias resistor
CL1,CL2
RS
CM
M
Table 5-5 32768Hz Oscillator Characteristics
Page 31
5.5. POWER UP AND POWER DOWN SEQUENCE

A31s supports four working modes: active mode, idle mode, super standby mode, and power-off mode.
PS
VCC-RTC
PWRIN delay
VCC-3V3
VDD-CPU
VDD-GPU
VDD-SYS
VCC-DRAM
AVCC
VCC-CPUS
PWROK delay
OFF delay
AP-RESET#
PMU-SCK
PMU-SDA
Others Power Supply
Timer
Debounce
PWRON
Figure 5-1
A31s Power Up/Down Sequence
Page 32
PIN ASSIGNMENT
PIN ASSIGNMENT
6.1. BALL MAP

1
NC
NC
NC
NC
NC
NC
NC
PC26
PH11
PH16
NC
PH10
PH15
PC27
NC
PH9
NC
PC11
PC24
PH20
PH24
PH17
PH21
PH25
PH14
PH18
PH22
PF0
PH13
PH19
10
11
12
PE1
PE8
PE0
PE3
PE9
PH26
NC
PE2
PH27
PH28
NC
13
14
15
PE13
PG0
PE11
PE14
PG1
PE10
PE12
PE15
JTAGSEL1
PE4
PE6
16
17
18
PG5
PG14
PG3
PG10
PG15
PG2
PG4
PG11
PE7
PG6
PG8
19
20
21
22
PB2
PB4
PB6
PB0
PB3
PB5
PB7
PG16
PB1
PA7
PA8
PA9
PG12
PG17
VCC-PB
PA4
PA13
NC
PC10
NC
PC15
PC14
PH12
VCC-PF
VCC-PC
PH23
UBOOT
JTAGSEL0
PE5
VCC-PE
VCC-PG
PG7
PG9
PG13
PG18
PA1
PA14
PA17
PA18
PC4
PC8
PC9
PC12
PC13
NC
NC
VCC-PC
VCC-PH
VCC-PH
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
CPU-VDDFB
PA0
PA3
PA16
PA19
PA20
PC0
PC5
PC6
PC7
NC
NC
GND
BOOTSEL1
BOOTSEL0
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
PA2
PA12
PA15
PA22
PF4
PF5
PC1
PC2
PC3
PC25
NC
GND
GND
GND
GND
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
PA5
PA11
PA21
PA23
PA26
SDQ2
SDQ6
PF1
PF2
PF3
VDD-GPU
VDD-GPU
GND
GND
GND
GND
GND
GND
GND
GND
VDD-CPU
VDD-CPU
PA6
PA10
PA25
PA24
PA27
SDQ4
SDQ0
SZQ
VDD-GPU
VDD-GPU
VDD-GPU
GND
GND
GND
GND
GND
GND
GND
GND
VDD-CPU
VDD-CPU
VRP
VRA1
VRA2
HPOUTR
SDQS0
SDQS0B
SDQ5
SDQM0
SRAS
VDD-GPU
VDD-GPU
GND
GND
GND
GND
GND
GND
GND
GND
VDD-CPUS
VDD-CPUS
AVCC
HPOUTL
MIC1P
PHINP
PHINN
SDQ7
SDQ3
SDQ1
SODT
SODT1
VDD-GPU
VDD-GPU
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC-PA
HPCOMFB
LINEINL
MIC1N
MIC2P
MIC2N
SDQ14
SDQ10
SCS1
SCAS
VDD-GPU
VDD-GPU
GND
GND
GND
GND
GND
GND
GND
GND
AGND
VCC-PA
HPCOM
LINEINR
MBIAS
HPBP
SDQ12
SDQ8
SDQ13
SDQM1
VDD-GPU
VCC-DRAM
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC-PD
VCC-HP
PHOUTN
PHOUTP
HBIAS
LINEOUTR
LINEOUTL
SDQS1
SDQS1B
SDQ11
SCS
SA2
VCC-DRAM
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC-PD
VCC-PD
PM1
PM0
PM2
PM4
LRADC0
SDQ15
SA3
SBA2
SCKE
VCC-DRAM
VCC-DRAM
GND
GND
GND
GND
VDD-SYS
VDD-SYS
VDD-SYS
VDD-SYS
VDD-SYS
VCC-USB
PM3
PM6
PM5
PM7
SDQ9
SBA0
SA0
SRST
SA10
VCC-DRAM
VCC-DRAM
VCC-DRAM
VDD-DLL
VDD-SYS
VDD-SYS
VDD-SYS
VDD-SYS
VDD-SYS
VDD-SYS
VDD-SYS
VCC-HDMI
VCC-PM
PL5
PL3
PL0
RESET
SWE
SA5
SCK
SA15
SBA1
VCC-DRAM
VCC-DRAM
SA8
SA6
SA11
PD27
PD25
PD23
PD9
PD7
PD5
PD3
PD1
VCC-RTC
PL8
X32KO
X32KI
SA7
SCKB
SA1
SVREF
SA12
VCC-DRAM
SA14
SA4
GND
PD26
PD24
PD22
PD8
PD6
PD4
PD2
PD0
NMI
PL7
PL2
SA9
SA13
SCKE1
SDQM2
SDQ17
SDQ30
SDQ26
SDQS3B
SDQ31
X24MO
HHPD
HTX1N
HSDA
HTX2N
PD20
PD19
PD21
PD10
PL6
PL4
DM0
DP0
AA
SDQ22
SDQ20
SDQS2
SDQ23
SDQ19
SDQ28
SDQS3
SDQ29
SDQ27
X24MI
HTXCN
HTX0P
HTX1P
HTX2P
PD16
PD18
PD15
PD13
PD11
VIO-RTC
DM1
DP1
AA
AB
SDQ18
SDQ16
SDQS2B
SDQ21
SDQ24
SDQ25
SDQM3
HTXCP
HTX0N
HSCL
PD17
PD14
PD12
PL1
DM2
DP2
AB
11
12
14
15
17
18
20
21
22
10
13
16
19
Page 33 / 34
PIN ASSIGNMENT
6.2.
PIN DIMENSION
Page 34 / 34

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A31s

January 30, 2013

THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE.

THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.

A31s Datasheet (Revision1.0)

Copyright 2013 Allwinner Technology. All Rights Reserved.

A31s Datasheet (Revision 1.0)

Copyright 2013 Allwinner Technology. All Rights Reserved.

BLOCK DIAGRAM ................................................................................................................................... 10

Pin Characteristics ............................................................................................................................. 11

GPIO Multiplexing Functions ............................................................................................................. 18

Detailed Pin/Signal Description ......................................................................................................... 22

Power/GND Signal Description ......................................................................................................... 27

ELECTRICAL CHARACTERISTICS ........................................................................................................ 29

Absolute Maximum Ratings ............................................................................................................... 29

Recommended Operating Conditions ............................................................................................... 29

DC Electrical Characteristics ............................................................................................................. 30

Oscillator Electrical Characteristics ................................................................................................... 30

Power up AND Power Down Sequence ............................................................................................ 32

PIN ASSIGNMENT ................................................................................................................................... 33

Ball map ............................................................................................................................................. 33

Pin Dimension .................................................................................................................................... 34

A31s Datasheet (Revision1.0)

Copyright 2013 Allwinner Technology. All Rights Reserved.

A31s Datasheet (Revision 1.0)

Copyright 2013 Allwinner Technology. All Rights Reserved.

- Support 16 SGIs, 16 PPIs, and 128 SPIs

- PowerVR SGX544MP2 GPU

- Support BLT and ROP2/3/4, scaling function with

- Real time registers for second, minute, hour, day,

- 6 timers: clock source can be switched over

A31s Datasheet (Revision1.0)

Copyright 2013 Allwinner Technology. All Rights Reserved.

DRC(dynamic range compression)

Comply to eMMC standard specification v4.5

and encoder can work at the same time

IMAGE SIGNAL PROCESSOR

image mirror flip and rotation

A31s Datasheet (Revision 1.0)

dual display paths

HDMI 1.4 1080p@60fps

Copyright 2013 Allwinner Technology. All Rights Reserved.

- Support sample rate up to 250Hz

parallel 12-bit CSI

ANALOG AUDIO INPUT

two audio ADC channels

ANALOG AUDIO OUTPUT

A31s Datasheet (Revision1.0)

- A flexible receiver for IR remote controller

- Comply to industry-standard 16450/16550 UART

- Up to 5 TWIs compliant with I2C protocol

Copyright 2013 Allwinner Technology. All Rights Reserved.

DES, 3DES, SHA-1, MD5

A31s Datasheet (Revision 1.0)

PLL clock generator and 32768Hz OSC

460 balls, 0.8mm ball pitch, 18mm x18mm

Copyright 2013 Allwinner Technology. All Rights Reserved.

Figure 3-1. A31s Block Diagram

A31s Datasheet (Revision1.0)

Copyright 2013 Allwinner Technology. All Rights Reserved.