LC2MOS, High Speed,

4-Channel/8-Channel 10-Bit ADCs

Data Sheet AD7777/AD7778
FEATURES FUNCTIONAL BLOCK DIAGRAMS
CLKIN VCC
AD7777: 4-channel
AD7778: 8-channel AIN1 CONTROL
AIN2 REGISTER
Fast 10-bit ADC AIN3 MUX T/H 10
ADCREG2
5 V supply AIN4
1 1
10-BIT ADCREG1 DB0 TO DB9
Half scale conversion option ADC 10

Fast interface port CREFIN

Power-down mode VBIAS
MUX T/H
2 2
APPLICATIONS REFIN
REF REFOUT
Instrumentation RTN VSWING
REFIN
AD7777
GENERAL DESCRIPTION CONTROL LOGIC AGND

01196-001
The AD7777/AD7778 are high speed, multichannel, 10-bit CS RD WR BUSY/INT DGND AGND
analog-to-digital converters (ADCs) primarily intended for use
Figure 1. AD7777
in R/W head positioning servos found in high density hard disk
CLKIN VCC
drives. They have unique input signal conditioning features that
make them ideal for use in such single-supply applications. AIN1 CONTROL
REGISTER
AIN2
By setting a bit in a control register within both the 4-channel AIN3 T/H
1 ADCREG2
10
AIN4
AD7777 and the 8-channel AD7778, the input channels can be AIN5
MUX
1 10-BIT ADCREG1
10
DB0 TO DB9
ADC
independently sampled or any two channels can be simultane- AIN6
AIN7 CREFIN
ously sampled. For both the AD7777 and AD7778, the specified AIN8
VBIAS
input signal range is VBIAS ± VSWING. However, if the RTN pin is T/H
biased at, for example, 2 V, the analog input signal range becomes MUX 2
REF
REFIN
REFOUT
2
0 V to 2 V for all input channels (see the Changing the Analog RTN VSWING

Input Voltage Range section). The bias voltage, VBIAS, is the offset of AGND
AD7778
the midpoint code of the ADC from ground and is supplied REFIN
CONTROL LOGIC
either by an onboard reference available to the user (REFOUT)

01196-002
or by an external voltage reference applied to REFIN. The full- CS RD WR BUSY/INT DGND AGND
scale range (FSR) of the ADC is equal to 2 × VSWING where Figure 2. AD7778
VSWING is nominally equal to REFIN/2. Additionally, when
placed in the half scale conversion mode, the value of REFIN is
converted, which allows the channel offsets to be measured.
Control register loading, ADC register reading, channel
selection, and the conversion start are under the control of the
microprocessor. The twos complement coded ADCs are easily
interfaced to a standard 16-bit microprocessor unit bus via their
10-bit data port and standard microprocessor control lines.
The AD7777/AD7778 are fabricated in linear compatible CMOS
(LC2MOS), an advanced, mixed technology process that
combines precision bipolar circuits with low power CMOS logic.
The AD7777 is available in a 28-lead, wide-body SOIC package.
The AD7778 is available in a 44-lead MQFP.

Rev. B Document Feedback

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AD7777/AD7778 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 CR6 ............................................................................................... 11
Applications ....................................................................................... 1 CR7 ............................................................................................... 11
General Description ......................................................................... 1 CR8 ............................................................................................... 11
Functional Block Diagrams ............................................................. 1 CR9 ............................................................................................... 11
Revision History ............................................................................... 2 ADC Conversion Start Timing................................................. 12
Specifications..................................................................................... 3 Track-and-Hold .......................................................................... 12
Timing Specifications .................................................................. 4 Power-Down ............................................................................... 12
Absolute Maximum Ratings............................................................ 6 Microprocessor Interfacing Circuits ........................................ 13
ESD Caution .................................................................................. 6 Applications Information .............................................................. 14
Pin Configurations and Function Descriptions ........................... 7 Digital Signal Processing Applications .................................... 14
Terminology ...................................................................................... 9 Layout Hints ................................................................................ 14
Theory of Operation ...................................................................... 10 ADC Corruption ........................................................................ 15
ADC Transfer Function ............................................................. 10 ADC Conversion Time .............................................................. 15
Control Register .............................................................................. 11 Outline Dimensions ....................................................................... 16
CR0 to CR2.................................................................................. 11 Ordering Guide .......................................................................... 16
CR3 to CR5.................................................................................. 11

REVISION HISTORY
4/2020—Rev. A to Rev. B Changes to Control Register Section ........................................... 11
Updated Format .................................................................. Universal Changes to ADC Conversion Start Timing Section .................. 12
Deleted AD7776.................................................................. Universal Changes to Microprocessor Interfacing Circuits Section ......... 13
Changes to Title, Features Section, Applications Section, and Changes to Changing the Analog Input Voltage Range Section ... 14
General Description section ........................................................... 1 Changed S/(N+D) to SINAD Throughout ................................. 15
Deleted Figure 1 and Patent Note; Renumbered Sequentially ... 1 Updated Outline Dimensions ....................................................... 17
Changed Plus or Minus Full-Scale Error to Positive or Negative Changes to Ordering Guide .......................................................... 17
Full-Scale Error Throughout........................................................... 3
Deleted AD7776 24-Lead SOIC Pin Configuration Figure ........ 4 10/2002—Rev. 0 to Rev. A
Added Timing Diagrams Section ................................................... 5 Changes to Specifications .................................................................2
Changes to Figure 5 .......................................................................... 5 Changes to Ordering Guide ............................................................4
Changes to Table 3 ............................................................................ 6 Changes to Total Harmonic Distortion, THD Section ............. 10
Added Table 5; Renumbered Sequentially .................................... 8 Changes to Outline Dimensions .................................................. 12
Deleted Figure 9; Renumbered Sequentially................................. 8

Rev. B | Page 2 of 16
Data Sheet AD7777/AD7778

SPECIFICATIONS
VCC = 5 V ± 5%; AGND = DGND = 0 V; CLKIN = 8 MHz; RTN = 0 V; CREFIN = 10 nF; all specifications TMIN to TMAX (−40°C to +85°C),
unless otherwise noted.

Table 1.
Parameter Symbol A Version Unit Test Conditions/Comments
DC ACCURACY
Resolution1 10 Bits max
Relative Accuracy ±1 LSB max See the Terminology section
Differential Nonlinearity ±1 LSB max No missing codes; see Terminology
Bias Offset Error ±12 LSB max See the Terminology section
Bias Offset Error Match 10 LSB max Between channels, see the Terminology section
Positive or Negative Full-Scale ±12 LSB max See the Terminology section
Error
Positive or Negative Full-Scale 10 LSB max Between channels, see the Terminology section
Error Match
ANALOG INPUTS
Input Voltage Range
All Inputs VBIAS ± VSWING V min/max
Input Current 200 µA max VIN = VBIAS ± VSWING; any channel
REFERENCE INPUT
REFIN 1.9/2.1 V min/max For specified performance
REFIN Input Current 200 µA max
REFERENCE OUTPUT
REFOUT 1.9/2.1 V min/max Nominal REFOUT = 2.0 V
DC Output Impedance 5 Ω typ
Reference Load Change ±2 mV max For reference load current change of 0 µA to ±500 µA
±5 mV max For reference load current change of 0 mA to ±1 mA,
do not change the reference load during conversion
Short Circuit Current2 20 mA max See the Terminology section
LOGIC OUTPUTS
DB0 to DB9, BUSY/INT
Output Low Voltage VOL 0.4 V max Since current (ISINK) = 1.6 mA
Output High Voltage VOH 4.0 V min Source current (ISOURCE) = 200 µA
Floating State Leakage ±10 µA max
Current
Floating State Capacitance2 10 pF max
ADC Output Coding Twos complement
LOGIC INPUTS
DB0 to DB9, CS, WR, RD, CLKIN
Input Low Voltage VINL 0.8 V max
Input High Voltage VINH 2.4 V min
Input Leakage Current 10 µA max
Input Capacitance2 10 pF max
CONVERSION TIMING
Acquisition Time 4.5 tCLKIN ns min See the Terminology section
5.5 tCLKIN + 70 ns max
Single Conversion 14 tCLKIN ns max
Double Conversion 28 tCLKIN ns max
Period of CLKIN Input Clock tCLKIN 125/500 ns
min/max
Minimum High Time for CLKIN 50 ns min
Minimum Low Time for CLKIN 40 ns min

Rev. B | Page 3 of 16
AD7777/AD7778 Data Sheet
Parameter Symbol A Version Unit Test Conditions/Comments
POWER REQUIREMENTS
VCC Range 4.75/5.25 V min/max For specified performance
Supply Current ICC
Normal Mode 15 mA max CS = RD = 5 V, CR8 = 0
Power-Down Mode 1.5 mA max CR8 = 1, all linear circuitry off
Power-Up Time to Operational 500 µs max From power-down mode
Specifications
DYNAMIC PERFORMANCE See the Terminology section
Signal-to-Noise-and-Distortion SINAD −56 dB min VIN = 99.88 kHz full-scale sine wave with sampling
Ratio frequency (fSAMPLING) = 380.95 kHz
Total Harmonic Distortion THD −60 dB min VIN = 99.88 kHz full-scale sine wave with fSAMPLING =
380.95 kHz
Intermodulation Distortion IMD −75 dB typ fa = 103.2 kHz, fb = 96.5 kHz with fSAMPLING = 380.95 kHz,
both signals are sine waves at half scale amplitude
Channel to Channel Isolation −90 dB typ VIN = 100 kHz full-scale sine wave with fSAMPLING =
380.95 kHz
1
1 LSB = (2 × VSWING)/1024 = 1.95 mV for VSWING = 1.0 V.
2
Guaranteed by design, not production tested.

TIMING SPECIFICATIONS
VCC = +5 V ± 5%; AGND = DGND = 0 V; all specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.

Table 2.
Parameter1, 2 Symbol Limit at TMIN to TMAX Unit Test Conditions/Comments
INTERFACE TIMING
CS Falling Edge to WR or RD Falling Edge t1 0 ns min
WR or RD Rising Edge to CS Rising Edge t2 0 ns min
WR Pulse Width t3 53 ns min
CS or RD Active to Valid Data3, 4 t4 60 ns max Timed from whichever occurs last
Bus Relinquish Time after RD3, 5 t5 10 ns min
45 ns max
Data Valid to WR Rising Edge t6 55 ns min
Data Valid after WR Rising Edge t7 10 ns min
WR Rising Edge to BUSY Falling Edge t8 1.5 tCLKIN ns min CR9 = 0
2.5 tCLKIN + 70 ns max
WR Rising Edge to BUSY Rising Edge or INT Falling Edge t9 19.5 tCLKIN + 70 ns max Single conversion, CR6 = 0
t10 33.5 tCLKIN + 70 ns max Double conversion, CR6 = 1
WR or RD Falling Edge to INT Rising Edge t11 60 ns max CR9 = 1
1
See Figure 3 to Figure 5.
2
All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
100% production tested. All other times are guaranteed by design, but not production tested.
4
t4 is measured with the load circuit of Figure 6 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5
t5 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 6. The measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. This means that t5 is the true bus relinquish time of the device and, as such, is independent of
the external bus loading capacitance.

Rev. B | Page 4 of 16
Data Sheet AD7777/AD7778
Timing Diagrams
t1 t2
CS

RD
t5
t4

01196-003
DB0 TO
DB9

Figure 3. Read Cycle Timing

t1 t2
CS

t3
WR
t7
t6

01196-004
DB0 TO
DB9

Figure 4. Write Cycle Timing

FIRST SECOND
CONVERSION CONVERSION
FINISHED FINISHED (CR6 = 1)
(CR6 = 0) AD7777/AD7778 ONLY
t3

WR, RD
t9
t8
BUSY
(CR9 = 0)
t10
t11
t9
INT
(CR9 = 1) 01196-005
t10

Figure 5. BUSY/INT Timing

1.6mA IOL

DB0 TO 2.1V
DB9
CL
100pF
01196-006

200µA IOH

Figure 6. Load Circuit for Bus Timing Characteristics

Rev. B | Page 5 of 16
AD7777/AD7778 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
Table 3. stress rating only; functional operation of the product at these
Parameter Rating or any other conditions above those indicated in the operational
VCC to AGND or DGND −0.3 V to +7 V section of this specification is not implied. Operation beyond
AGND, RTN to DGND −0.3 V to VCC + 0.3 V the maximum operating conditions for extended periods may
CS, RD, WR, CLKIN, DB0 to DB9, BUSY/INT −0.3 V to VCC + 0.3 V affect product reliability.
to DGND
Analog Input Voltage to AGND −0.3 V to VCC + 0.3 V ESD CAUTION
REFOUT to AGND −0.3 V to VCC + 0.3 V
REFIN to AGND −0.3 V to VCC + 0.3 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOIC Package, Power Dissipation 875 mW
θJA Thermal Impedance 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
MQFP Package, Power Dissipation 500 mW
θJA Thermal Impedance 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Rev. B | Page 6 of 16
Data Sheet AD7777/AD7778

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DB0 1 28 CREFIN
DB1 2 27 AGND
NC 3 26 RTN
DB2 4 25 REFIN
DB3 5 24 AIN4
DGND 6
AD7777 23 AIN3
TOP VIEW
DB4 7 (Not to Scale) 22 AIN2
DB5 8 21 AIN1
DB6 9 20 AGND
DB7 10 19 REFOUT
DB8 11 18 VCC
(MSB) DB9 12 17 CLKIN
BUSY/INT 13 16 WR
RD 14 15 CS

01196-007
NOTES
1. NC = NO CONNECT.

Figure 7. AD7777 Pin Configuration

Table 4. AD7777 Pin Function Descriptions

Pin No. Mnemonic Description
1, 2, 4, 5, 7 to 12 DB0 to DB9 Input/Output Data Bus. This is a bidirectional data port from which ADC output data can be read and to
which control register data can be written. DB9 is the MSB.
3 NC No Connect.
6 DGND Digital Ground. DGND is the ground reference for the digital circuitry.
13 BUSY/INT Busy/Interrupt Output. Active low logic output indicating ADC status. This logic output has two modes
of operation, depending on whether CR9 of the control register is set low or high, as follows:
If CR9 is set low, the BUSY/INT output behaves as a BUSY signal. The BUSY signal goes low and stays low
for the duration of a single conversion. If simultaneous sampling is selected, BUSY stays low for the
duration of both conversions.
If CR9 is set high, BUSY/INT output behaves as an interrupt signal. The INT signal goes low and remains
low after either a single conversion is completed or after a double conversion is completed if
simultaneous sampling is selected. With CR9 high, the falling edge of WR or RD resets the INT line high.
14 RD Read Input (Active Low). RD is used in conjunction with CS to enable the data outputs from the ADC
registers.
15 CS Chip Select Input. The device is selected when this input is low.
16 WR Write Input (Active Low). WR is used in conjunction with CS to write data to the control register. Data is
latched to the registers on the rising edge of WR. Following the rising edge of WR, the analog input is
acquired and a conversion is started.
17 CLKIN Clock Input.
18 VCC 5 V Power Supply.
19 REFOUT Voltage Reference Output. This pin provides the internal voltage reference, which is nominally 2.0 V.
REFOUT provides the bias voltage (VBIAS) for the input channels.
20, 27 AGND Analog Ground.
21 to 24 AIN1 to AIN4 Analog Input 1 to Analog Input 4. The analog input range is VBIAS ± VSWING, where VBIAS and VSWING are
defined by the reference voltage applied to REFIN. Input resistance between any of the analog input pins
and AGND is 10 kΩ or greater.
25 REFIN Voltage Reference Input. The AD7777 is specified over a voltage reference range of 1.9 V to 2.1 V with a
nominal value of 2.0 V. This REFIN voltage provides the VBIAS and VSWING levels for the input channels. VBIAS
is equal to REFIN, and VSWING is nominally equal to REFIN/2. Input resistance between this REFIN pin and
AGND is 10 kΩ or greater.
26 RTN Signal Return Path for Input Channels. Normally, RTN is connected to AGND at the package.
28 CREFIN Reference Decoupling Capacitor. A 10 nF capacitor must be connected from this pin to AGND to ensure
correct operation of the high speed ADC.

Rev. B | Page 7 of 16
AD7777/AD7778 Data Sheet

CREFIN

REFIN
AGND
RTN
DB1
DB0
NC
NC

NC
NC

NC
44 43 42 41 40 39 38 37 36 35 34

NC 1 33 AIN8
NC 2 32 AIN7
DB2 3 31 AIN6
DB3 4 30 AIN5
DGND 5 AD7778 29 AIN4
DB4 6 TOP VIEW 28 AIN3
(Not to Scale)
DB5 7 27 AIN2
DB6 8 26 AIN1
DB7 9 25 AGND
NC 10 24 REFOUT
NC 11 23 VCC

12 13 14 15 16 17 18 19 20 21 22

WR
CLKIN
NC
NC

NC

RD
CS

NC
DB8
(MSB) DB9

BUSY/INT

01196-008
NOTES
1. NC = NO CONNECT.

Figure 8. AD7778 Pin Configuration

Table 5. AD7778 Pin Function Descriptions

Pin No. Mnemonic Description
1, 2, 10, 11 to NC No Connect.
13, 16, 22, 34,
39, 40, 43, 44
3, 4, 6 to 9, 14, DB0 to Input/Output Data Bus. This is a bidirectional data port from which ADC output data can be read and to
15, 41, 42 DB9 which control register data can be written. DB9 is the MSB.
5 DGND Digital Ground. DGND is the ground reference for the digital circuitry.
17 BUSY/INT Busy/Interrupt Output. Active low logic output indicating ADC status. This logic output has two modes of
operation depending on whether CR9 of the control register is set low or high, as follows:
If CR9 is set low, the BUSY/INT output behaves as a BUSY signal. The BUSY signal goes low and stays low
for the duration of a single conversion. If simultaneous sampling is selected, BUSY stays low for the
duration of both conversions.
If CR9 is set high, BUSY/INT output behaves as an interrupt signal. The INT signal goes low and remains
low after either a single conversion is completed or after a double conversion is completed if
simultaneous sampling is selected. With CR9 high, the falling edge of WR or RD resets the INT line high.
18 RD Read Input (Active Low). RD is used in conjunction with CS to enable the data outputs from the ADC
registers
19 CS Chip Select Input. The device is selected when this input is low.
20 WR Write Input (Active Low). WR is used in conjunction with CS to write data to the control register. Data is
latched to the registers on the rising edge of WR. Following the rising edge of WR, the analog input is
acquired and a conversion is started.
21 CLKIN Clock Input.
23 VCC 5 V Power Supply.
24 REFOUT Voltage Reference Output. This pin provides the internal voltage reference, which is nominally 2.0 V.
REFOUT provides the bias voltage (VBIAS) for the input channels.
25, 37 AGND Analog Ground.
26 to 33 AIN1 to AIN8 Analog Input 1 to Analog Input 8. The analog input range is VBIAS ± VSWING, where VBIAS and VSWING are defined
by the reference voltage applied to REFIN. Input resistance between any of the analog input pins and
AGND is 10 kΩ or greater.
35 REFIN Voltage Reference Input. The AD7778 is specified over a voltage reference range of 1.9 V to 2.1 V with a
nominal value of 2.0 V. This REFIN voltage provides the VBIAS and VSWING levels for the input channels. VBIAS is
equal to REFIN, and VSWING is nominally equal to REFIN/2. Input resistance between this REFIN pin and
AGND is 10 kΩ or greater.
36 RTN Signal Return Path for Input Channels. Normally RTN is connected to AGND at the package.
38 CREFIN Reference Decoupling Capacitor. A 10 nF capacitor must be connected from this pin to AGND to ensure
correct operation of the high speed ADC.

Rev. B | Page 8 of 16
Data Sheet AD7777/AD7778

TERMINOLOGY
Relative Accuracy Short-Circuit Current
For the AD7777/AD7778, relative accuracy or endpoint Short-circuit current is defined as the maximum current that
nonlinearity is the maximum deviation, in LSBs, of the actual flows either into or out of the REFOUT pin if this pin is shorted
code transition points of the ADC from a straight line drawn to any potential between 0 V and VCC. This condition can be
between the endpoints of the ADC transfer function. allowed for up to 10 sec provided that the power dissipation of
Differential Nonlinearity the package is not exceeded.
Differential nonlinearity is the difference between the measured Signal-to-Noise-and-Distortion (SINAD) Ratio
change and the ideal 1 LSB change between any two adjacent SINAD is the ratio of the rms value of the measured input
codes. A specified maximum differential nonlinearity of ±1 LSB signal to the rms sum of all other spectral components below
ensures no missed codes. the Nyquist frequency, including harmonics, but excluding dc.
Bias Offset Error The value for SINAD is given in decibels.
For an ideal 10-bit ADC, the output code for an input voltage Total Harmonic Distortion, THD
equal to VBIAS is midscale. The bias offset error is the difference Total harmonic distortion is the ratio of the rms sum of the first
between the actual midpoint voltage for midscale code and five harmonic components to the rms value of a full-scale input
VBIAS, expressed in LSBs. signal and is expressed in decibels. For the AD7777/ AD7778,
Bias Offset Error Match total harmonic distortion (THD) is defined as
Bias offset error match is a measure of how closely the bias
offset errors of all channels track each other. The bias offset 20 log
(V
2
2
+ V32 + V4 2 + V52 + V6 2 )
V1
error match of any channel must be no further away than
10 LSBs from the bias offset error of any other channel, where:
regardless of whether the channels are independently sampled V1 is the rms amplitude of the fundamental.
or simultaneously sampled. V2, V3, V4, V5, and V6 are the rms amplitudes of the individual
Positive and Negative Full-Scale Error harmonics.
The input channels of the ADC can be considered to have Intermodulation Distortion, IMD
bipolar (positive and negative) input ranges, but are referred to With inputs consisting of sine waves at two frequencies, fa and fb,
VBIAS (or REFIN) instead of AGND. Positive full-scale error for any active device with nonlinearities creates distortion products, of
the ADC is the difference between the actual input voltage order (m + n), at sum and difference frequencies of mfa + nfb,
required to produce the positive full-scale code transition and where m and n = 0, 1, 2, 3. Intermodulation terms are those for
the ideal input voltage (VBIAS + VSWING −1.5 LSB), expressed in which m or n is not equal to zero. For example, the second-
LSBs. Negative full-scale error is similarly specified for the order terms include (fa + fb) and (fa – fb) and the third-order
minus full-scale code transition, relative to the ideal input terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb), and (fa – 2 fb).
voltage for this transition (VBIAS − VSWING + 0.5 LSB). Note that Channel to Channel Isolation
the full-scale errors for the ADC input channels are measured Channel to channel isolation is a measure of the level of
after their respective bias offset errors have been adjusted out. crosstalk between channels. It is measured by applying a full-
Positive and Negative Full-Scale Error Match scale 100 kHz sine wave signal to any one of the input channels
Positive and negative full-scale error match is a measure of how and monitoring the remaining channels. The figure given is the
closely the full-scale errors of all channels track each other. The worst case across channels.
full-scale error match of any channel must be no further than
10 LSBs from the respective full-scale error of any other
channel, regardless of whether the channels are independently
sampled or simultaneously sampled.

Rev. B | Page 9 of 16
AD7777/AD7778 Data Sheet

THEORY OF OPERATION
ADC TRANSFER FUNCTION 1FF
1FE

For the AD7777/AD7778, an input signal of the form VBIAS ±

VSWING is expected. This VBIAS signal level operates as a

ADC OUTPUT CODE (HEX)

pseudoground to which all input signals must be referred. The
VBIAS level is determined by the voltage applied to the REFIN
pin. The REFIN pin can be driven by an external voltage source 000
or, alternatively, by the on-board 2 V reference, available at
REFOUT. The magnitude of the input signal swing is equal to
VBIAS/2 (or REFIN/2) and is set internally. With a REFIN of 2 V,
the analog input signal level varies from 1 V to 3 V, that is,
2 ± 1 V. Figure 9 shows the transfer function of the ADC and its 202
201
relationship to VBIAS and VSWING. The half scale twos complement 200
code of the ADC (0x000 or 00 0000 0000 binary), occurs at an VBIAS

01196-009
input voltage equal to VBIAS. The input FSR of the ADC is equal VBIAS – VSWING
ANALOG INPUT, VIN
VBIAS + VSWING

to 2 VSWING, so that the positive full-scale transition (0x1FE to Figure 9. ADC Transfer Function
0x1FF) occurs at a voltage equal to VBIAS + VSWING − 1.5 LSBs,
and the negative full-scale code transition (0x200 to 0x201)
occurs at a voltage = VBIAS − VSWING + 0.5 LSBs.

Rev. B | Page 10 of 16
Data Sheet AD7777/AD7778

CONTROL REGISTER
The control register is 10 bits wide and can only be written to. CR6
On power-on, all bit locations in the control register are
automatically loaded with 0s. For the quad channel AD7777, CR6 determines whether operation is on a single channel or
CR2 and CR5 are don’t care bits. Individual bit functions are simultaneous sampled on two channels.
described in the following sections. Table 10.
CR0 TO CR2 CR6 Description
CR0 to CR2 determine which channel is selected and converted 0 Single-channel operation. The channel select address is
contained in CR0 to CR2.
for single-channel operation. For simultaneous sampling
1 Two channels simultaneously sampled and sequentially
operation, CR0 to CR2 hold the address of one of the two converted. The channel select addresses is contained in
channels to be sampled. CR0 to CR2 and CR3 to CR5.
Table 6. AD7777 CR0 to CR2 Bit Descriptions CR7
CR2 CR1 CR0 Description CR7 determines whether the device is in the normal operating
X1 0 0 Select AIN1 mode or in the half scale test mode.
X1 0 1 Select AIN2
X1 1 0 Select AIN3 Table 11. CR7 Bit Descriptions
X1 1 1 Select AIN4 CR7 Description
0 Normal operating mode
1
X means don’t care. 1 Half scale test mode
Table 7. AD7778 CR0 to CR2 Bit Descriptions In the half scale test mode, REFIN is internally connected as an
CR2 CR1 CR0 Description analog input. In this mode, CR0 to CR2 and CR3 to CR5 are all
0 0 0 Select AIN1 don’t care bits because it is REFIN that is converted. For the
0 0 1 Select AIN2 AD7777 and AD7778, the contents of CR6 still determine
0 1 0 Select AIN3 whether a single or a double conversion is carried out on the
0 1 1 Select AIN4 REFIN level.
1 0 0 Select AIN5
CR8
1 0 1 Select AIN6
1 1 0 Select AIN7 CR8 determines whether the device is in the normal operating
1 1 1 Select AIN8 mode or in the power-down mode.

CR3 TO CR5 Table 12. CR8 Bit Descriptions

CR3 to CR5 are only applicable for simultaneous sampling with CR8 Description
the AD7777 or AD7778 when CR3 to CR5 hold the address of 0 Normal operating mode
the second channel to be sampled. 1 Power-down mode
In the power-down mode, all linear circuitry is turned off and
Table 8. AD7777 CR3 to CR5 Bit Descriptions
the REFOUT output is weakly (5 kΩ) pulled to AGND. The
CR5 CR4 CR3 Description
input impedance of the analog inputs and of the REFIN input
X1 0 0 Select AIN1
remains the same in either normal mode or power-down mode
X1 0 1 Select AIN2
(see the Power-Down section).
X1 1 0 Select AIN3
X1 1 1 Select AIN4 CR9
CR9 determines whether the BUSY/INT output flag goes low
1
X means don’t care.
and remains low during conversions or goes low and remains
Table 9. AD7778 CR3 to CR5 Bit Descriptions low after the conversions are complete.
CR5 CR4 CR3 Description
0 0 0 Select AIN1
Table 13. CR9 Bit Descriptions
0 0 1 Select AIN2 CR9 BUSY/INT Functionality
0 1 0 Select AIN3 0 Output goes low and remains low during conversions.
0 1 1 Select AIN4 1 Output goes low and remains low after conversions are
1 0 0 Select AIN5 complete.
1 0 1 Select AIN6
1 1 0 Select AIN7
1 1 1 Select AIN8
Rev. B | Page 11 of 16
AD7777/AD7778 Data Sheet
ADC CONVERSION START TIMING POWER-DOWN
Figure 10 shows the operating waveforms for the start of a The AD7777/AD7778 can be placed in a power-down mode
conversion cycle. On the rising edge of WR, the conversion simply by writing a logic high to CR8 of the control register.
cycle starts with the acquisition and tracking of the selected The following changes are effected immediately upon writing a
ADC channel, AIN1 to AIN8. The analog input voltage is held 1 to CR8:
40 ns (typically) after the first rising edge of CLKIN following • Any conversion in progress is terminated.
four complete CLKIN cycles. If tD (time between WR rising and • If a conversion is in progress, the leading edge of WR
the first falling edge of CLKIN, as shown in Figure 10) is greater immediately drives the BUSY/INT output high.
than 12 ns, the falling edge of CLKIN is seen as the first falling
• All the linear circuitry is turned off.
clock edge. If tD is less than 12 ns, the first falling clock edge to
• The REFOUT output stops being driven and is weakly
be recognized does not occur until one cycle later.
(5 kΩ) pulled to analog ground.
Following the hold on the analog inputs, two complete CLKIN
cycles are elapse for settling purposes before the conversion of The control inputs (CS, WR, and RD) retain their functions as
the MSB is completed. The conversion of the MSB occurs inputs while the AD7777/AD7778 are in power-down mode. If
approximately 40 ns after the rising edge of CLKIN, as shown in no conversions are in progress when the AD7777/AD7778 are
Figure 10. It takes up to two more CLKIN cycles for the second placed into power-down mode, the contents of the ADC
MSB conversion. The succeeding bit decisions are made registers, ADCREG1 and ADCREG2, are retained during
approximately 40 ns after each rising edge of CLKIN until the power-down and can be read as normal. On returning to
conversion is complete. normal operating mode, a new conversion (or conversions,
dependent on CR6) is automatically started. Upon completion,
At the end of conversion, if a single conversion is requested
the invalid conversion results are loaded into the ADC registers,
(CR6 = 0), the BUSY/INT line changes state (as programmed by
losing the previous valid results.
CR9) and the successive approximation register (SAR) contents
are transferred to ADC Register 1, ADCREG1. The SAR is then To achieve the lowest possible power consumption in the
reset in readiness for a new conversion. If simultaneous power-down mode, attention must be paid to the state of the
sampling is requested (CR6 = 1), no change occurs in the status digital and analog inputs and outputs, as follows:
of the BUSY/INT output, and the ADC automatically starts the • Because each analog input channel is connected to AGND
second conversion. At the end of this conversion, the BUSY/INT via a resistive divider (the input resistance of which does
line changes state (as programmed by CR9) and the SAR not change between normal and power-down modes),
contents are transferred to ADC Register 2, ADCREG2. driving the analog input signals to 0 V or as close as
possible to 0 V minimizes the power dissipated in the input
WR
tD1
signal conditioning circuitry.
• Similarly, the REFIN input is connected to AGND via a
CLKIN resistive divider, the input resistance of which does not
40ns
TYP
40ns
TYP
change between normal and power-down modes. If an
VIN external reference is being used, driving this reference
CHANNEL
input to 0 V or as close as possible to 0 V minimizes the
ACQUISITION power dissipated in the input signal conditioning circuitry.
01196-010

HOLD DB9 (MSB)

1TIMING SHOWN FOR t GREATER THAN 12ns • Because the REFOUT pin is typically pulled to AGND via
D
a 5 kΩ resistor, any voltage greater than 0 V to which this
Figure 10. ADC Conversion Start Timing
output may be pulled by external circuitry dissipates
TRACK-AND-HOLD unnecessary power.
The track-and-hold amplifiers on the analog inputs of the • Hold all digital inputs (CS, WR, and RD) at VCC or as close
AD7777/AD7778 allow the ADC to accurately convert an input as possible. Hold CLKIN as close as possible to either 0 V
sine wave of 2 V p-p amplitude up to a frequency of 189 kHz, or VCC.
the Nyquist frequency of the ADC when operated at its • Because the BUSY/INT output is actively driven to a logic
maximum throughput rate of 378 kHz. This maximum rate of high, any loading on this pin to 0 V dissipates power.
conversion includes conversion time and the time between The AD7777/AD7778 comes out of the power-down mode
conversions. Because the input bandwidth of the track-and- when a Logic 0 is written to CR8 of the control register. Note
hold is much greater than 189 kHz, the input signal must be that the contents of the other bits in the control register are
band limited to avoid folding unwanted signals into the band of retained when the device is placed in power-down and are valid
interest. when power is restored. However, coming out of power-down

Rev. B | Page 12 of 16
Data Sheet AD7777/AD7778
provides an opportunity to reload the complete contents of the A15 TO A0 ADDRESS BUS AD7777/
control register without any extra instructions. IS AD77781
READY ADDR
MICROPROCESSOR INTERFACING CIRCUITS MSC
DECODE CS

The AD7777/AD7778 family of ADCs is intended to interface STRB

WR
R/W
to digital signal processors (DSPs) such as the TMS320 family RD
and microcontrollers such as the 80C196 family. DB9 TO DB0
TMS320C25-40
Figure 11 shows the AD7777/AD7778 interfaced to the
D15 TO D0 DATA BUS
TMS320C10 at 20.5 MHz and the TMS320C14 at 25 MHz.

01196-012
Figure 12 shows the interface with the TMS320C25 at 40 MHz. 1ADDITIONAL PINS OMITTED FOR CLARITY.
Note that one wait state is required with this interface. Figure 12. AD7777/AD7778 to TMS320C25 Interface
Figure 13 shows the interface with the 80C196KB at 12 MHz AD15 TO AD6
ADDRESS BUS
(PORT 4)
and the 80C196KC at 16 MHz. One wait state is required with
the 16 MHz microcontroller. The 80C196 is configured to ‘373
ALE LATCH AD7777/
operate with a 16-bit multiplexed address/data bus. AD77781
80C196KB-12 ADDR
80C196KC-16 DECODER CS
Table 14 provides a truth table for the AD7777/AD7778 and
summarizes their microprocessor interfacing features. Note that WR WR
RD RD
a read instruction to any of the devices while a conversion is in
AD7 TO AD0
progress immediately stops that conversion and returns (PORT 3) DATA BUS DB9 TO DB0

01196-014
unreliable data over the data bus. 1ADDITIONAL PINS OMITTED FOR CLARITY.

A11 TO A0 ADDRESS BUS AD7777/ Figure 13. AD7777/AD7778 to 80C196KB/802C196KC Interface

AD77781
TMS320C10-20.5 ADDR
TMS320C14-25 DECODE CS
WE WR
(C10) DEN RD
(C14) REN
DB9 TO DB0

D15 TO D0 DATA BUS

01196-011

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 11. AD7777/AD7778 to TMS320C10 and TMS320C14 Interface

Table 14. AD7777/AD7778 Truth Table for Microprocessor Interfacing

CS RD WR DB0 to DB9 Function/Comments
1 X1 X1 High Z Data port high impedance
0 1 High to low CR Data Load control register data to the control register and start a conversion.
0 Low to high 1 ADC data ADC data placed on data bus. Depending upon CR6 of the control register,
one or two read instructions are required.
If CR6 is low, that is, with single-channel conversion selected, a read
instruction returns the contents of ADCREG1. Succeeding read instructions
continue to return the contents of ADCREG1.
If CR6 is high, that is, simultaneous sampling (double conversion) selected,
the first read instruction returns the contents of ADCREG1, whereas the
second read instruction returns the contents of ADCREG2. A third read
instruction returns ADCREG1 again, the fourth ADCREG2, and so on.
1
X means don’t care.

Rev. B | Page 13 of 16
AD7777/AD7778 Data Sheet

APPLICATIONS INFORMATION
DIGITAL SIGNAL PROCESSING APPLICATIONS The effective number of bits vs. input frequency for a single
In digital signal processing application areas like voice channel of the AD7777/AD7778 is shown in Figure 15. The
recognition, echo cancellation, and adaptive filtering, the effective number of bits is typically 9.5.
10.0
dynamic characteristics (SINAD, THD, and IMD) of the ADC SAMPLE FREQUENCY = 378.4kHz
TA = 25°C
are critical. The AD7777/AD7778 are specified dynamically as
well as with standard dc specifications. Because the track-and- 9.5

EFFECTIVE NUMBER OF BITS

hold amplifier has a wide bandwidth, place an antialiasing filter
on the analog inputs to avoid aliasing high frequency noise back 9.0
into the bands of interest.
The dynamic performance of the ADC is evaluated by applying 8.5
a sine wave signal of very low distortion to a single analog input
which is sampled at 380.95 kHz. A fast Fourier transform (FFT)
plot or histogram plot is then generated from which the SINAD, 8.0

harmonic distortion, and dynamic differential nonlinearity data

can be obtained. Similarly, for intermodulation distortion, an 7.5

01196-016
0 189.2
input signal consisting of two pure sine waves at different INPUT FREQUENCY (kHz)
frequencies is applied to the AD7777/AD7778.
Figure 15. Effective Number of Bits vs. Input Frequency
Figure 14 shows a 2048-point FFT plot for a single channel of
Changing the Analog Input Voltage Range
the AD7777/AD7778 with an input signal of 99.88 kHz. The
SNR is 58.7 dB. Figure 14 shows that most of the harmonics are By biasing the RTN pin above AGND, it is possible to change
buried in the noise floor. The harmonics are taken into account the analog input voltage range from its VBIAS ± VSWING format to
when calculating the SINAD. a more traditional 0 V to reference voltage range. The new input
0 range can be described as offset voltage (VOFFSET) to (VOFFSET +
INPUT FREQUENCY =
99.88kHz REFIN), where 0 V ≤ VOFFSET ≤ 1 V.
SAMPLE FREQUENCY =
380.95kHz
SNR = 58.7dB
To produce this range, the RTN pin must be biased to (REFIN −
–20
TA = 25°C 2 × VOFFSET). For instance, if RTN is tied to REFOUT, the analog
SIGNAL AMPLITUDE (dB)

input range becomes 0 V to 2 V. The fixed 2 V analog input

–40 voltage span of the ADC can range from 1 V to 3 V (RTN =
0 V) to 0 V to 2 V (RTN = 2 V), that is, with proper biasing, an
input signal range from 0.3 V to 2.3 V can be covered. Both the
–60
relative accuracy and differential nonlinearity performance
remain essentially unchanged in this mode, whereas the SNR
–80
and THD performance are typically 2 dB to 3 dB worse than
typical.
–90
01196-015

0 99.88
LAYOUT HINTS
FREQUENCY (kHz)

Figure 14. ADC FFT Plot

Ensure that the digital and analog grounds are separated as
much as possible in the layout for the printed circuit board.
The relationship between SINAD and resolution (n) is Take care not to run any digital tracks along an analog signal
expressed by the following equation: track. Guard (screen) the analog inputs with RTN.
SINAD = (6.02n + 1.76) dB (1) Establish a single-point analog ground separate from the logic
This equation is for an ideal device with no differential or system ground and as close as possible to the AD7777/AD7778.
integral linearity errors. These errors cause a degradation in Connect both the RTN and AGND pins on the AD7777/AD7778
SINAD. By working backward from Equation 1, it is possible to and all other signal grounds to this single-point analog ground.
measure the ADC performance expressed in effective number In turn, connect this star ground to the digital ground at one
of bits (n). point only, preferably at the low impedance power supply itself.
SINAD − 1.76 Low impedance analog and digital power supply common
n ( effective ) = returns are important for correct operation of the devices.
6.02
Therefore, make the foil width for these tracks as wide as
where SINAD is given in decibels. possible.

Rev. B | Page 14 of 16
Data Sheet AD7777/AD7778
To ensure a low impedance 5 V power supply at the actual VCC Executing a write instruction to the AD7777/AD7778 while a
pin, it is necessary to use bypass capacitors from the pin itself to conversion is in progress immediately halts the conversion
DGND. A 4.7 µF tantalum capacitor in parallel with a 0.1 µF when the falling edge of WR is driving the BUSY/INT output
ceramic capacitor is sufficient. high. The analog input is sampled as normal, and a new
ADC CORRUPTION conversion sequence (dependent upon CR6) starts.

Executing a read instruction to the AD7777/AD7778 while a ADC CONVERSION TIME

conversion is in progress immediately halts the conversion and Although each conversion takes only 14 CLKIN cycles, it can
returns invalid data over the data bus. Monitor the BUSY/INT take between 4.5 and 5.5 CLKIN cycles to acquire the analog
output pin closely and prevent all read instructions to the inputs after the WR input goes high and before any conversions
AD7777/AD7778 when this output shows that a conversion is start.
in progress.

Rev. B | Page 15 of 16
AD7777/AD7778 Data Sheet

OUTLINE DIMENSIONS
18.10 (0.7126)
17.70 (0.6969)

28 15
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
14
10.00 (0.3937)

0.75 (0.0295)
45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 1.27 (0.0500) 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
BSC 0.31 (0.0122) 0.40 (0.0157)
0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AE

06-07-2006-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 16. 28-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
14.15
1.03 2.45 13.90 SQ
0.88 MAX 13.65
0.73
44 34
1.95 REF 1 33

SEATING
PLANE
10.20
TOP VIEW 10.00 SQ
(PINS DOWN)
9.80
2.10
2.00 0.23
1.95 0.11
11 23
0.25 7° 12 22
0.15 0°
0.10 0.45
0.10
COPLANARITY 0.30
VIEW A 0.80 BSC LEAD WIDTH
LEAD PITCH
06-10-20014-B

VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MO-112-AA-2

Figure 17. 44-Lead Metric Quad Flat Package [MQFP]

(S-44-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range No. of Channels Package Description Package Option
AD7777ARZ −40°C to +85°C 4 28-Lead Standard Small Outline Package [SOIC_W] RW-28
AD7777ARZ-REEL −40°C to +85°C 4 28-Lead Standard Small Outline Package [SOIC_W] RW-28
AD7778ASZ −40°C to +85°C 8 44-Lead Metric Quad Flat Package [MQFP] S-44-2
1
Z = RoHS Compliant Part.

©2018–2020 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D01196-4/20(B)

Rev. B | Page 16 of 16