Exar Function Generator Data Book
Exar Function Generator Data Book
10V Temperature. 300 600 _| ppm/°c_| _ Sweep input open circuit Frequency Sweep Range 7A To:1 See Figure 7 ‘Output Swing: Single Ended Fe 3 Yep Measured at pin 1 or 2 Differential 4 6 Yop Measured across 1 and 2 Output Diff. Offset Voltage ol 04 _| vac Measured across 1 and 2 “Amplitude Control Range 60 B. Controlled by Rg (see Figure 1) Buffer Amplifier Output Resistance 30 ohms RL = 7500 Output Current Swing Ed Zo mA TI— Output Waveforms Sinusoidal: ‘Upper Frequency Limit a 4 Miz Measured at Pin 11 Peak Output Swing 2 3 pp S1, 83 closed, $2 open Distortion (THD) 28 4 |e ‘closed $2 open Triangle Peak Swing 2 4 pp Measured at Pin 11 Non-Linearity Fa % S1, $2 open, S3 closed Asymmetry 41 % f= 10 kHz Sawtooth: Peak Swing 2 3 Yep See Figure 1, $2 closed; Non-Linearity 15 & Sp and $3 closed Ramp: Peak-Swing 1 14 ep See Figure 1, $2 and $3 open ‘Non-Linearity 1 % pin 10 shorted to pin 15 ‘Squarewave (Low Level): Output Swing 0.5 07 Yep See Figure 1, $2 and $3 open, Duty Cycle Asymmetry A 4 | % pin 10 shorted to pin 12 Rise Time 20 as 10 pF connected from pin 11 Fall Time 20 ns to ground ‘Squarewave (High Level) Peak Swing 2 5 Yop See Figure 3, $2 open Duty Cycle Asymmetry 4 “4 | % Rise Time 80 as 10 pF connected from pin 11 Fall Time 60 ns. to ground Pulse Output: 2 3 ‘Vp See Figure 3, $2 closed Peak Swing 2 3 Yop See Figure 3, $2 closed Rise Time 80 as Fall Time 60 as Duty Cycle Range 20:80 % ‘Adjustable (eee Figure 6) = Modulation Characteristics (ine, triangle and squarewave): “Amplitude Modulation: Double Sideband Modulation Range 0-100 % See Figure 2 Linearity 0.5 % ‘for 30% modulation Sideband Symmetry 10 % Suppressed Cartier Carrier Suppression 52 4B £<1 Miz Frequency Modulation: Distortion 03 % See Figure 2 (+10 frequency deviation) "TEST CIRCUITS Figure 2 Test Circuit for S} AM/EM Modulation JUL “= JUL Sere Sa II coms nema on Figure 3, Test Circuit for High-Level Pulse and Squarewave Output 2 DESCRIPTION OF CIRCUIT CONTROLS (Refer to functional block diagram) ‘TIMING CAPACITOR (PINS 14 AND 15) ‘The oscillator frequency is inversely proportional to the value of the timing capacitor, C,, connected between pins 14 and 15. With the sweep input open circuited, frequency f, can be Teproxinated tf = 400/C, where & win He aad C, isin mieroforads, (See Figure 4.) MODULATOR Y-INPUTS (PINS 5 AND 6) ‘These inputs are normally connected to the oscillator outputs. For sinewave or trianglewave outputs, they are de coupled to pins 14 and 15 (see Figure 1); for high-level squarewave or pulse output, ac coupling is used as shown in Figure 3. MODULAR X-INPUTS (PINS 3 AND 4) age applied across these inputs — (see Figure 5). These inputs can be used for amplitude modulation or, as an output ampli- tude control. The phase of the output voltage is reversed if the polarity of the de bias across pins 3 and 4 is reversed; therefore these inputs can be used for phase-shift keyed (PSK) modula tion, MODULATOR OUTPUTS (PINS 1 AND 2) All of the high level output waveforms are obtained at these terminals. The output waveforms appear differentially between pins | and 2, The terminals can, therefore, be used for either in-phase or out-of-phase outputs. Normally, a 15 KS load resistor should be connected between these terminals to pre vent the output from saturating or clipping at large output voltage swings. LOW LEVEL SQUAREWAVE OUTPUT (PIN 12) ‘The output at this pin is a symmetrical squarewave with 0.7V amplitude and 20 ns rise time. It can be used directly as an out: put waveform, or amplified to a 3 Vpp signal level using the ‘modulator ection of the XR-205 as an amplifier (see Figure 3), SWEEP OR FM INPUT (PIN 13) ‘The oscillator frequency increases linearly with an increasing negative voltage, Vs, applied to this terminal. Normally a series resistor, Ry (Rs ~ approx. 1 KO) is connected in series with this terminal to provide current limiting and linear voltage-to- frequency transfer characteristics. The frequency derivation (for any given modulation level) is inversely proportional to Rg. Typical sweep characteristics of the circuit are shown in Figure 7. For proper operation of the circuit with Rx = 1 KQ, the swesp voltage, Vs, must be within range: (Vso ~ 6) < Vg <(Vsq + 1) where Vso is the open circuit voltage at pin 13. The frequency of oscillation can also be synchronized to an external source by applying a syne pulse to this terminal. For Rg = 1 KO, a syne pulse of 0.1V to 1V amplitude is recom- mended WAVEFORM ADJUSTMENT (PINS 7 AND 8) ‘The shape of the output waveform at pins 1 and 2 is controlled by a potentiometer, Rj, connected between these terminals as shown in Figure 1. For sinewave outputs at pins 1 and 2, the value of Rj is adjusted to minimize the harmonic content of the output waveform. This adjustment is independent of frequency and needs to be done only once. The output can be converted to a symmetrical triangle waveform by increasing the effective resistance across these terminals. This can be done without changing the potentiometer setting, by opening the switch $2 as shown in Figures 1-3.Figure 7, Normalized Frequency vs. ‘Sweep Voltage “ e 3 ow E T 1 ie z entouney | He i tog eed i = +e 2 i i | a - : i : F He: ee me fei cetas i“ 37) | eect i Nj ee ! | ; ea ww? 2 te ar ° 20 rc 72 gure 4: Freguencyas4 Function of Co PigueS, Modulator Section Pave and Figure 6, Duty Cycle and Frequency ‘tos ins 1 and 13 ‘Rtiode Transfer Characteristics Visnton aos Povetion of Restor : 4 Conosted Acrots Ps 13 and 14 m4 a oT our =a ne aes 5, eal IN i i i : r L g { é i a NAAN 2 hs act 5, | : d He Figure 8, Sinusoidal Output Distorition aa Function of Frequency Sweep Figure 9. Sinusoidal Sawtooth and Linear Ramp Outputs @ BUFFER INPUT AND OUTPUT (PINS 10 AND 11) ‘The buffer amplifier can be connected to any of the circuit outputs (pins 1, 2, 12, 14 or 15) to provide low output im- pedance and high current drive capability.For proper operation of the buffer amplifier, pin 11 must be connected to the most negative potential in the circuit, with an external load resistor Ry (0.75 KQ10Ka. [Oscillator Section Max. Operating Frequency as er neat muiz | C1000 pF, R1=1 KO Lowest Practical Frequency 0.01 0.01 Hz | C=50 uF, Ry=2 M@ Frequency Accuracy a1] 44 2 % of fo] fg= W/RIC ‘Temperature Stability +10} 350 +20| —_ |ppm/*C| °c ) ted tie BR 1-S)] me i | R13 where Vc is in volts, The voltage-to-frequency conversion sain, K, is given as: 0.32 K= ance. aneve=- Rag HV NOTE: For safe operation of the circuit I should be limited to mA. 16 Figure 10, Circuit Connection for Frequency Sweep OUTPUT CHARACTERISTICS: Output Amplitude: Maximum output amplitude is directly porportional to external resistor R3 connected to Pin 3 (See Fig. 3). For sinowave output, amplitude is approximately 60 mV peak per KS of R3; for triangle, the peak amplitude is approximately 160 mV peak per K{2 of R3. Thus, for example, R3 = 50 KQ would produce epproximately +3V sinusoidal output amplitude. ‘Amplitude Modulation: Output amplitude can be modulated by applying a dc bias and a modulating signal to Pin 1. The internal impedance at Pin 1 is approximately 100 KO. Output amplitude varies linearly with the applied voltage at Pin 1, for valuet of de bias at this pin, within +4 volts of V+/2 as shown in Fig. 6, As this bias level approaches V*/2, the phase of the output signal is reversed; and the amplitude goes through zero. ‘Tais property is suitable for phase-chift keying and suppressed- carrier AM generation. Total dynamic range of amplitude modulation is approximately 55 4B. Note: AM control must be used in conjunction with a well- regulated supply since the output amplitude now becomes a function of V*. FREQUENCY-SHIFT KEYING ‘The XR-2206 can be operated with two separate timing resis- tors, Ry and Rz, connected to the timing pins 7 and 8, respec- tively, as shown’ in Figure 13. Depending on the polarity of the logic signal at pin 9, either one or the other of these timingresistors is activated, If pin 9 is open-circuited or connected to fa bias voltage > 2V, only Ry is active. Similarly, if the voltage Ievel at pin 9 is < IV, only R2 is activated. Thus, the output frequency. can be keyed between two levels, f and f as’ £1 = 1/R1C and £2 = 1/RoC For split-supply operation, the keying voltage at pin 9 is referenced to V-. OUTPUT DC LEVEL CONTROL ‘The dc level at the output (pin 2) is approximately the same as the de bias at pin 3. In Figures 11, 12 and 13, pin 3 is bissed mid-way between V+ and ground, to give an output dclevel of =V*/2. APPLICATIONS INFORMATION SINEWAVE GENERATION ‘A) Without External Adjustment Figure 11 shows the circuit connection for generating a sinusoidal output from the XR-2206. The potentiometer Rj at pin 7 provides the desired frequency tuning. The ‘maximum output swing is greater than V+/2 and the =o 'y €L08 FOR SEWAVE, [Figure 11, Circuit for Sinewave Generation Without External ‘Adjustment. (See Fig. 3 for choice of Ry) typical distortion (THD) is < 2.5%. If lower sinewave dis- tortion is desired, additional adjustments can be provided as described in the following section. The circuit of Figure 11 can be converted to split supply operation simply by replacing all ground connections with V™=. For split supply operation, R3 can be directly connected to ground. 'B) With External Adjustment ‘The harmonic content of sinusoidal output can be reduced to ©0.5% by additional adjustments as shown in Figure 12. The potentiometer Ra adjusts the sine-shaping resistor; Figure 12, Circuit for Sinewave Generation With Minimum Harmonic Distortion. (R Determines output Swing ~ See Fig. 3) 7 and Rp provides the fine-adjustment for the waveform symmetry. The adjustment procedure is as follows: 1, Set Rp at mid-point and adjust Ra for minimum dis- tortion. 2. With Ra set as above, adjust Rp to further reduce distortion. ‘TRIANGLE WAVE GENERATION ‘The circuits of Figures 11 and 12 can be converted to triangle wave generation by simply open circuiting pins 13 and 14 (ie., S1 open). Amplitude of the triangle is approximately twice the sinewave output. FSK GENERATION Figure 13 shows the circuit connection for sinusoidal FSK signal generation. Mark and space frequencies can be indepen- dently adjusted by the choice of timing resistors Ry and Ro; ‘and the output is phase-continuous during transitions. The keying signal is applied to pin 9. The circuit can be converted to split-supply operation by simply replacing ground with V~. Figure 13, Sinusoidal PSK Generator PULSE AND RAMP GENERATION Figure 14 shows the circuit for pulse and ramp waveform generation. In this mode of operation, the FSK keying termi- nal (pin 9) is shorted to the square-wave output (pin 11); and the circuit automatically frequency-shift keys itself between two seperate frequencies during the positive and negative going output waveforms. The pulse-width and the duty cycle can be adjusted from 1% to 99% by the choice of Rj and R2. The values of Rj and R2 should be in the range of 1 K@. to 2M.XR-2207 Voltage - Controlled Oscillator GENERAL DESCRIPTION ‘The XR-2207 is a monolithic voltage-controlled oscillator (VCO) integrated circuit featuring excellent frequency stability and a tuning range. The circuit provides simultaneous triangle and squarewave outputs over a frequency range of 0.01 Hz to 1 MHz. Itis ideally suited for FM, FSK, and sweep or tone generation, as well as for phase-locked loop applications. The circuit is comprised of four functional blocks: a variable-frequency oscillator which generates the basic periodic waveforms; four current switches actuated by binary keying inputs; and buffer amplifiers for both the triangle and squarewave outputs. The internal current switches transfer the oscillator current to any of four external timing resistors to produce four discrete frequencies which are selected according to the binary logic levels at the keying terminals (pins 8 and 9). ‘The XR-2207 has a typical drift specification of 20 ppm/°C. The oscillator frequency can be linearly swept over a 1000:1 range with an external control voltage; and the duty cycle of both the triangle and the squarewave outputs can be varied from 0.1% to 99.9% to generate stable pulse and sawtooth waveforms. FEATURES ABSOLUTE MAXIMUM RATINGS Excellent Temperature Stability (20 ppm/*C) Power Supply 26V Linear Frequency Sweep Pape: Dison onsen ni ton) il Adjustable Duty Cycle (0.1% to 99.9 ceramic pac z 750 m Taser Fou Losi FER Canty | eras above +25°C somwre ie Plastic package 625 mW Wide Sweep Range (1000:1 Min) eee ree a Logic Compatible Input and Output Levels Wide Supply Voltage Range (4V to £13V) Low Supply Sensitivity (0.15%/V) Wide Frequency Range (0.01 Hz to 1 MHz) AVAILSELE TYEES ‘Simultancous Triangle and Squarewave Outputs Storage Temperature Range 65°C to #150°C feilee .. \nteligeatl peatgreabesas APPLICATIONS ‘XR2207M. Ceramic =55°C to +125°C FSK Generation XR2207N Ceramic °C to 475°C vi i al ss Ciencia XR2207P Plastic O°C to 75°C Vole and Curent toFreasency Hasren ee wewrre ‘Weseform Geneevtion XR2207CP Plastic 0°C to +75°C Tage davis es Sadap rand Sep Gonrtion EQUIVALENT SCHEMATIC DIAGRAM FUNCTIONAL BLOCK DIAGRAM Fay sepnnenae ran paler Fa Figure 1 18ELECTRICAL CHARACTERISTICS ‘Test Conditions: Test Cireuit of Figure 1, Vt = 6V, Ta = #25°C, C Binary Inputs grounded, S, and Sz closed unless otherwise specified. 000 pF, Ri = 2 Ra = Ry = 20 KO, RL=4.7 KS XR-2207/XR-2207M XR-2207C PARAMETERS RET Rare MLAS IN | TERS TAN ee CONDITIONS GENERAL CHARACTERISTICS ‘Supply Voltage Single Supply 8 apd. 98: 26| Vv See Figure 2 Split Supplies +4 43] 44 +B] V See Figure 3 Supply Current Single Supply Bi) hol 5} 8] mA | Measured at pin 1,S, and S: open, see Figure 2 Split Supplies : Positive Sle? 5s} 8] ma | Measured at pin 1, $;, $2 open Negative 4] 6 4| 7] mA | Measured at pin 12,1, $2 open ‘OSCILLATOR SECTION — FREQUENCY CHARACTERISTICS Upper Frequency Limit os] 10 os] 10 Miz | C=500pF,R Lowest Practical Frequency 001 001 Hz _ | C=S0uF,R,=2M2 Frequency Accuracy “| 3 Hi] #5 | Hoffe Frequency Matching 05 os Hot fo Frequency Stability ‘Temperature 20 50 30 ppm/*C} 0° (Measured at Pin 12) vs. Supply voltage Voltase i : 2 TP = i a = : aan : i a i Figure 7. Recommended Timing Resistor Value vs. Power Supply Veltage® es ae j. , hel ice pte i. Raley 2 laa zl pias i Bo] gia | lel i- Tr Seal wre 8. Frequency Accuracy vs, Timing Resistance Figure 9. Frequency Drift vs. Supply Voltage Figure 10, Normalized Frequency Drift With Temperature *Note: Ry’ = Parallel Combination of Activated Timing Resistorsa ‘The circuit operates with supply voltages ranging from + 4V to £13V. Minimum drift occurs with 26 volt supplies. For operation with unequal supply voltages, see Figure 6. lLocic | SELECTED|FREQUENCY| ILEVEL| TIMING PINS. AB DEFINITIONS oof 6 It T/R3C, Af oO 1[ 6ana7 [fi +Aty 1/R2C, Of 0 fScn lel [Logic Levels: 0 11] 4ands_ [+n 1 Figure 11. Logic Table For Binary Keying Controls. Note: For Single-Supply Operation, Logic Levels are Referenced to Voltage at Pin 10 DEEL. Figure 12, Simplified Schematic of Frequency Control Mechanism The logic levels at the keying inputs (pins 8 and 9) are refer- enced to ground, A logic “0” corresponds to a keying voltage Vi < LAV, and a logic “1” corresponds to Vx >3V. An ‘open circuit at the keying inputs also corresponds to a “0” level. SINGLE SUPPLY OPERATION ‘The circuit should be interconnected as shown in Figure 14 for single supply operation. Pin 12 should be grounded, and pin 11 biased from V* through a resistive divider to a value Of bias voltage between V*/3 and V*/2. Pin 10 is bypassed to ground through 1 HF capacitor. For single supply operation, the de voltage at pin 10 and the timing terminals (pins 4 through 7) are equal and approxi mately 0.6V below Vp, the bias voltage at pin 11. The logic levels at the binary keying terminals are referenced to the For a fixed frequency of £3 = 1/R3C, the external circuit connections can be simplified as shown in Figure 14b. SELECTION OF EXTERNAL COMPONENTS: TIMING CAPACITOR (PINS 2 AND 3) ‘The oscillator frequency is inversely proportional to the ‘timing capacitor, C, as indicated in Figure 11. The minimum ‘capacitance value is limited by stray capacitances and the Figure 13, SplitSupply Operation: (a) General (b) Fixed Frequency ‘maximum value by physical size and leakage current con- siderations. Recommended values range from 100 pF to 100 uF. ‘The capacitor should be non-polar. TIMING RESISTORS (PINS 4, 5, 6, AND 7) ‘The timing resistors determine the total timing current, Ir, available to charge the timing capacitor. Values for timing resistors can range from 2 K@ to 2 M&2; however, for opti- mum temperature and power supply stability, recommended values are 4 KO to 200 KO (see Figures 7,9, and 10). To svoid parasitic pick up, timing resistor leads should be Kept 4s short as possible, For noisy environments, unused, or deactivated timing terminals should be bypassed to ground through 0.1 AF capacitors. SUPPLY VOLTAGE (PINS 1 AND 12) ‘The XR-2207 is designed to operate over a power supply range of 14V to 13V for spit supplies, oF BV t0 26V for single supplies. At high supply voltages, the frequency sweep range is reduced (see Figures 6 and 7). Performance is optimum for #6V, or 12V single supply operation BINARY KEYING INPUTS (PINS 8 AND 9) ‘The internal impedance at these pins is approximately 5 KQ. Keying levels are < 1.4V for “zero” and > 3V for “one” logic levels. referenced to the de voltage at pin 10 (Gee Figure 11).BIAS FOR SINGLE SUPPLY (PIN 11) For single supply operation, pin 11 should be externally biased to a potential between V*/3 and V*/2 volts (see Figure 14). The total oscillation timing current, Fy. jas current at pin 1 is nominally $% of the seusne nave (a) General (b) Fixed Frequency ca rrasscararton BIR pend. Figure 15, Frequency Sweep Operation ods Figure 16, Alternate Frequency Sweep Operation GROUND (PIN 10) For split supply operation, this pin serves as cireult ground. For single supply operation, pin 10 should be ac grounded through a | uF bypass capacitor. During split supply opera tion, a ground current of 2Iy flows out of this terminal, where Ir is the total timing current SQUAREWAVE OUTPUT (PIN 13) ‘The squarewave output at pin 13 is a “open-collector” stage capable of sinking up to 20 mA of load current. Ry serves ‘asa pull-up load resistor for this output. Recommended values for Ry, range from 1 KS to 100 KO. ‘TRIANGLE OUTPUT (PIN 14) ‘The output at pin 14 is a triangle wave with a peak swing of approximately one-half of the total supply voltage. Pin 14 has avery low output impedance of 10 @ and is internally pro- tected against short circuits BYPASS CAPACITORS The recommended value for bypass capacitors is 1 uF, although larger values are required for very low frequency operation. FREQUENCY CONTROL (SWEEP AND FM) ‘The frequency of operation is controlled by varying the total timing current, It, drawn from the activated timing pins 4, 5, 6, or 7. The timing current can be modulated by applying @ control voltage, Vc, to the activated timing pin through a series resistor R¢ as shown in Figures 15 and 16. For split supply operation, a negative control voltage, VC, applied to the circuits of Figures 15 and 16 causes the total timing current, I, and the frequency, to increase ‘Asan example, in the circuit of Figure 15, the binary keying inputs are grounded. Therefore, only timing pin 6 is activated. l 3c” portional to the control voltage, Vc, and determined as: Vor: opi [jm lisa ig R3C Rev- ‘The frequency of operation, normally is now pro-‘The frequency f will increase as the control voltage is made ‘more negative. If R3 = 2 MQ, Re = 2 K&2, C= 5000 pF, then ee 2 1000:1 frequency sweep would result for a negative sweep a voltage Vo ~ V- ‘The voltage to frequency conversion gain, K, is controlled by the series resistance Rc and can be expressed as: ar 1 ¥" Avo ~~ ReCV= Hzjvolt ‘The circuit of Figure 15 can operate both with positive and negative values of control voltage. However, for positive values of Ve with small (R¢/R3) ratio, the direction of the timing current [7 is reversed and the oscillations will stop. Ergare 16 shows alfstoste Grou for ferguenoyicostrol ee rhe two timing ping 6 and 7, are activated, ‘The fre pe eee ee before, except that the circuit would operate only with nega tive values of Vc. For V¢ > 0, pin 7 becomes deactivated 1 and the Frequency is Fixed at = goa CAUTION For operation of the circuit, total timing current It must be less than 6 mA over the frequency control range. DUTY CYCLE CONTROL ‘The duty cycle of the output waveforms can be controlled by frequency shift keying at the end of every half cycle of oscil lator output. This is accomplished by connecting one or both | of the binary keying inputs (pins 8 or 9) to the squarewave | output at pin 13. The output waveforms can then be converted | to positive or negative pulses and sawtooth waveforms. Figure 17 is the recommended circuit connection for duty cycle control, Pin 8 is shorted to pin 13 so that the circuit switches between the "0, 0””and the ‘1, 0” logic states given, in Figure 11. Timing pin 5 is activated when the output is “high,” and the timing pin is activated when the squarewave output goes t0 a low state. The duty cycle of the output waveforms is given as: and can be varied from 0.1% to 99.9% by proper choice of, timing resistors. The frequency of oscillation, f, is given as: ce Figure 18. Output Waveforms: peodefous (a) Squarewave and Triangle Outputs C [Ro+ Ra (b) Pulse and Sawtooth Outputs (©) Frequency-Shift Keyed Output Top: FSK Output With f= 2) The frequency can be modulated or swept without changing eee the duty cyele by connecting Rz and R3 to 8 common control voltage VG, instead of to V~ (see Figure 15). The sawtooth ‘TWO-CHANNEL FSK GENERATOR tnd the puise output waveforms are shown in Figure 18. (MODEM TRANSMITTER) ON — OFF KEYING ‘The multilevel frequency shift-keying capability of XR-2207 makes it ideally suited for two-channel FSK generation. A The XR-2207 can be keyed on and off by simply activating Tecommended circuit connection for this pplication irsnown an open circuited timing pin, Under certain conditions, the in Figure 19. circuit may exhibit very low frequency (<1 Hz) residual cxcillations in the “off” state due to internal bias current. For two-channel FSK generation, the “mark” and “space” If ths effect is undesirable, it can be eliminated by connect. frequencies of the respective channels are determined by the ing a 10 MQ resistor from pin 3 to V¥ timing resistor pairs (R, R2) and (R3, Ra). Pin Bis the 24Figure 19. Multi-Channel FSK Generation “‘channel-select” control in accord with Figure 11. For a “high” logic level at pin 8, the timing resistors Ry and R2 are activated, Similarly, for a “low” logic level, timing resisiors 3 and Rg are enabied, ‘The “high” and “low” logic levels at pin 9 determine the respective high and low frequencies within the selected FSK channel, Recommended component values for various commonly used FSK frequencies are given in Table I. When only a single FSK channel is used, the remaining channel can be deactivated by connecting pin 8 to either V* or ground. In this case, the unused timing resistors ean also be omitted from the circuit ‘The low and high frequencies, fy and f, for a given FSK chan- nel can be fine tuned using potentiometers connected in series with respective timing resistors, In fine tuning the fre- ‘quencies, f] should be set first with the logic level at pin 9 ina “low” level, ‘Typical frequency drift of the circuit for 0°C to 75°C opera tion is #0.2%. Since the frequency stability is directly related to the external timing components, care must be taken (0 use timing components with low temperature coef FSK TRANCEIVER (FULL-DUPLEX MODEM) ‘The XR-2207 can be used in conjunction with the XR-210, FSK demodulator, to form a full-duplex FSK transceiver, of Modem. A recommended circuit connection for this applica- tion is shown in Figure 20. Table I shows the recommended component values for 300-Baud (103-type) and 1200-Baud (202-type) Modem applications ‘OPERATING | TYPICAL COMPONENT | VALUES CONDITIONS encom 300 Baud XR-210 XR2207 Low Band. f= 1070He | Ro= 5.1 KO, C= 0.22uF | R3= 91k f)= 1270 Hz | Cy = C= 0.047 uF, Rg = 470k oan C3 = 0.033 uF a High Band Ro=8.2kM,Co= 0.1 pF | R3= 47k C) = C= C3 = 0.033 uF 470k 1200 Baud TRH, Co=O14HF [Ry = 75K fy = 1200 He | Cj = 0.033 uP, Be * 0.02 uF f= 2200 Mz | C= 0.01 uF Table 1. Recommended Component Values for Full Duplex FSK Modem of Figure 20 25 Figure 20. Full Duplex FSK Modem Using XR-210 and XR-2207 (See Table I For Component Values)XR-2209 Precision Oscillator GENERAL DESCRIPTION ‘The XR-2209 is a monolithie variable frequency oscillator circuit featuring excellent temperature stability and a wide linear sweep range. The circuit provides simultaneous triangle and squarewave outputs over a frequency range of 0.01 Hz to 1 MHz. The fre- quency is set by an external RC product. Iti ideally suited for frequency modulation, voltage to frequency or current to frequency ‘conversion, sweep or tone generation as well as for phase-locked loop applications when used in conjunction with a phase comparator such as the XR-2208. ‘The circuit is comprised of three functional blocks: a varigble frequency oscillator which generates the basic periodic waveforms and two buffer amplifiers for the triangle and the squarewave outputs. The oscillator frequency is set by an extemal capacitor, C, and the timing resistor R. With no sweep signal applied, the ffequency of oscillation is equal to 1/RC. The XR-2209 has a typical drift specification of 20 ppm/°C. Its frequency can be linearly swept over a 1000:1 range with an external control signal. FEATURES ABSOLUTE MAXIMUM RATINGS: iture Stability (20 °C) Power Supply 26 volts pieanatica oad Power Dissipation (package imitation) Linear Frequency Sweep mien tse Wide Sweep Range (1000:1 Min) Plastic Package 300 mW Wide Supply Voltage Range (24V to +13V) Derate above #25°C 2.5 mW/'C Low Supply Sensitivity (0.15%/V) ‘Temperature Range Wide Frequency Range (0.01 Hz to 1 MHz) Operating ‘ : Simultaneous Triangle and Squarewave Outputs XR-2300M —ssig to 8c Storage 65°C to 150°C APPLICATIONS AVAILABLE TYPES Voltage and Curront-to-Frequency Conversion peter Ree ele cas Stable Phase-Locked Loop XR-2209M Ceramic 55°C to +125°C Waveform Generation XR-2209CN Ceramic 0°C to +75°C FM and Sweep Generation XR-2209CP Plastic 0°C to #75°C. EQUIVALENT SCHEMATIC DIAGRAM FUNCTIONAL BLOCK DIAGRAM 26ELECTRICAL CHARACTERISTICS — PRELIMINARY Test Conditions: Test Citcuit of Figure 1, V* = V~ = 6V, Ta = #28°C,C= $000 pF, R= 20KA, RL =4.7 KA. 1 and $2 closed unless otherwise specified. PARAMETERS a =o units conpiTions 9 Se GENERAL CHARACTERISTICS Supply Valiage Single Supply 8 w% | 8 a Iv See Figure? Split Supplies 44 a3 | a4 a3 |v. | seeriue1 Supply Current single Supply Sa) cay s | 5 [ma | measured a pin 1, 81,52 open See Figure 2 Split Supplies Positive sees s | 8 [ma | measured at pin 1, $1, $2 open Negative 4|isabs 4 | 7_ [ma | measured at pin 481,89 open (OSCILLATOR SECTION — FREQUENCY CHARACTERISTICS Upper Frequency Linit os] 10 os 10 Miz [=500pF,R=2Ka, Lowest Practical Frequency oot oot Hz | C=S0ur,R= Frequescy Accuracy als 1 | 4s [mort Frequency Stability si F ‘Temperature 20) $0 30 ppm/"C_ | 0° 41V (Note: Triangle wave output ‘has +0.6V offtet with respect to ground.) Terminals 2, 3, and 4 have very low internal impedance and should, therefore, be protected from accidental short- ing to ground or the supply voltages. Triangle waveform linearity is sensitive to parasitic coup- ling between the square and the triangle-wave outputs (pins 7 and 8). In board layout or circuit wiring care should be taken to minimize stray wiring capacitances between these pins.9 DESCRIPTION OF CIRCUIT CONTROLS ‘TIMING CAPACITOR (PINS 2 and 3) ‘The oscillator frequency is inversely proportional to the timing capacitor, C. The minimum capacitance value is limited by stay capacitances and the maximum value by physical size and leakage current considerations. Recommended values range from 100 pF to 100 uF. The capacitor should be ‘non-polar. TIMING RESISTOR (PIN 4) ‘The timing resistor determines the total timing current, Tp, available to charge the timing capacitor. Values for the timing resistor can range from 1.5 KQ to 2 MQ; however, for optimum temperature and power supply stability, rec: ommended values are 4 KS to 200 KQ (see Figures 4, 7, and 8). To avoid parasitic pick up, timing resistor leads should be kept as short as possible. SUPPLY VOLTAGE (PINS 1 AND 6) ‘The XR-2209 is designed to operate over a power supply range of 44V to 13V for split supplies, or 8V to 26V for single supplies. At high supply voltages, the frequency sweep range is reduced (see Figures 3 and 4). Performance is optimum for £6V, or 12V single supply operation. BIAS FOR SINGLE'SUPPLY (PIN 5) For single supply operation, pin 5 should be externally biased to a potential between V*/3 and V*/2 volts (see Figure 9). The bias current at pin 5 is nominally 5% of the total oscillation timing current, IT, at pin 4. This pin should be bypassed to ground with 0.1 wF capacitor. SQUAREWAVE OUTPUT (PIN 7) ‘The squarewave output at pin 7 is a “open-collector” stage capable of sinking up to 20 mA of load current. RL serves as a pull-up load resistor for this output. Recommended values for RL range from 1 KQ to 100 KQ. ‘TRIANGLE OUTPUT (PIN8) The output at pin 8 is a triangle wave with a peak swing of approximately one-half of the total supply voltage. Pin 8 has a very low output impedance of 109 and is internally protected against short circuits. OPERATING INSTRUCTIONS ‘SPLIT SUPPLY OPERATION ‘The recommended circuit for split supply operation is shown in Figure 10. Diode Dy in the figure assures that the triangle output swing at_pin 8 is symmetrical about ground. This circuit operates with supply voltages ranging from *4V to 2 13V. Minimum drift occurs at £6V supplies. See Figure 3 for opera mn with unequal supplies. Simplified Connection For operation with split supplies in excess of £7 volts, the simplified circuit connection of Figure 11 can be used. This circuit eliminates the diode Dj used in Figure 10;however the triangle wave output at pin 8 now has a +0.6 volt DC offset with respect to ground, SINGLE SUPPLY OPERATION ‘The recommended circuit connection for single-supply opera- tion is shown in Figure 9. Pin 6 is grounded; and pin 5 is Figure 12. Frequency Sweep Operation biased from V+ through a resistive divider, as shown in the figure, and is bypassed to ground with a | uF capacitor. For single supply operation, the DC voltage at, the timing terminal, pin 4, is approximately 0.6 volts above VB, the bias voltage at pin 5. ‘The frequency of operation is determined by the timing capa citor C and the timing resistor R, and is equal to 1/RC. The squarewave output is obtained at pin 7 and hasa peak-to-peak voltage swing equal to the supply voltage. This output is an “opencollector” type and requires an external pull-up load resistor (nominally 5 KQ2) to V*. The triangle waveform ob- tained at pin 8 is centered about a voltage level VO where: Vo=VB+0.6v where Vi is the bis voltage at pin 5, The peaktopeak output swing of triangle wave is approximately equal to V¥/2. FREQUENCY CONTROL (SWEEP AND FM) The frequency of operation is proportional to the total timing current IT drawn from the timing pin, pin 4. This timing cur- rent, and the frequency of operation can be modulated by applying a control voltage, VC, to the timing pin, through series resistor, Rg, as shown in Figure 12. If Vc is negative with respect to Vi, the voltage level at pin 4, then an addi tional current Ig is drawn from the timing pin causing I to increase, thus increasing the frequency. Conversely, ma Vc higher than Va causes the frequency to decrease by decreasing Ir. The frequency of operation, is determined by: ety fie B-¥OR tro irag Meas] where fo = 1/RC.XR-8038 Precision Waveform Generator GENERAL DESCRIPTION ‘The XR-8038 is a precision waveform generator IC capable of producing sine, square, triangular, sawtooth and pulse waveforms with a minimum number of external components and adjustments. Its operating frequency can be selected over nine decades of frequency, from 0.001 Hz to 1 MHz, by the choice of external R-C components. The frequency of oscillation is highly stable over a wide range of temperature and supply voltage changes. The frequency control, sweep and modulation can be accomplished with an external control voltage, without effecting the quality of the output waveforms. Each of the three basic waveforms, ic. sinewave, triangle and square wave outputs are available simultaneously, from independent output terminals. The XR-8038 monolithic waveform generator uses advanced processing technology and Schottky-barrier diodes to enhance its frequency performance. It can be readily interfaced with a monolithic phase-detector circuit, such as the XR-2208, to form stable phase-locked loop circuits. FEATURES Direct Replacement for Intersil 8038 Low Frequency Drift-50 ppm/*C Max. Simultaneous Sine, Triangle and Square-Wave Outputs Low Distortion “THD ~ 1% High FM and Triangle Linearity Wide Frequency Range — 0.001 Hz to 1 MHz Variable Duty Cycle — 2% to 98% ABSOLUTE MAXIMUM RATINGS Power Supply 36v Power Dissipation (package limitation) Ceramic package 750 mW Derate above +25°C 6.0 mWw/PC Plastic package 625 mW Derate above +25°C 5 mw/°C Storage Temperature Range 65°C to #150°C APPLICATIONS AVAILABLE TYPES: Precision Waveform Generation Sine, Triangle, Square, Pulse Part Number Package Operating Temperature Sweep and FM Generation XR8038M Ceramic -55°C to #125°C Tone Generation XR-8038N Ceramic 0°C to +75°C Instrumentation and Test Equipment Design Ps ea ees Precision PLL Design XR-8038CN Ceramic 0°C 10 475°C ‘XR-8038CP Plastic 0°C to +75°C PACKAGE INFORMATION FUNCTIONAL BLOCK DIAGRAM « oie a We xn038ELECTRICAL CHARACTERISTICS Test Conditions: V; = 45V to #15V, Ta = 25°C, RL = 1 MO, Ra = Rp = 10K, Cy = 3300 pF, $1 closed, unless otherwise speci fied. See Test Circuit of Figure 1. XR-803: XR-8038C CHARACTERISTICS MING LIP MAK Tne ave Tuas], UNITE | CONDITIONS GENERAL CHARACTERISTICS [Supply Voltage, Vs Single Supply 10 30 | 10 30] Vv Dual Supplies 35 ais | 35 us| v Supply Current 12 [is 12 | 20 | _mA_| V,=#10V.See Note 1. FREQUENCY CHARACTERISTICS (Measured at Pin 9) Range of Adjustment Max. Operating Frequency 1 1 Miz} Ra=Rg=5009,C RL=1Sk2 Lowest Practical Frequency 0.001 0.001 Ha | Ra=Rp=1M9,C =500 uF Max. FM Sweep Frequency 100 100 kHz FM Sweep Range hooo:1 1000: $1 Open. See Notes 2 and 3. FM Linearity Ol 02 % | $1 Open. See Note 3. Range of Timing Resistors 0.5 1000] 0.5 1000] k9 | Values of Ra and Rp. Temperature Stability XR-8038M 20 | 50} - | - | - | ppmitc XR8038 so | 100] - | - | — | ppmi?c XR-8038C -|-|- 50 ppm/°C Power Supply Stability 0.05 0.05 GV _| See Note 4. ‘OUTPUT CHARACTERISTICS Square-Wave Measured at Pin 9. Amplitude 09 | 098 09 | 098 xVs Saturation Voltage 02 | 04 o2}os | v Rise Time 100 100 nsec Fall Time 40 40 see Duty Cycle Adi. 2 98 | 2 gs | % Triangle/Sawtooth/ Ramp Measured at Pin 3. Amplitude 03 | 033 03 | 033 xVs | RL=100k2 Linearity 0.05 On % Output Impedance 200 200 Tout = SmA ‘Sine-Wave Amplitude 02 [0.22 02 | 0.22 xVs | RL= 100K Distortion Unadjusted o7 | 15 08 | 3 | % | RL=1MO. See Notes. Adjusted os os ge __|Rr=i Mo Note 1: Currents through Ra and Rg not included. Note 2: Vs= 20V, Note 3: Apply sweep voltage at Pin 8. (2/3 Vg + 2V) < Voweep < Vs Note 4: 10V < Vs <30V or #5V< Vs <#I15V. Note 5: 81 k® resistor connected between Pins 11 and 12. 10 kHz, Ra = Rg = 10k. Figure 1. Generalized Test Circuit. 3CHARACTERISTIC CURVES an “77 Bs 3094 Tt no's t q = a & | : fat tt 3 islstl SMG LL etter i LT % oe) ‘Supply Voltage Power Dissipation vs. Supply Voltage Supply Voltage Frequency Dui vs. Power Supply ‘Sinewave THD vs. Frequency WAVEFORM ADJUSTMENT The symmetry of all waveforms can be adjusted with the external timing resistors. Two possible ways to accomplish this are shown in Figure 2. Best results are obtained by keeping the timing resistors Ra and Rp separate (a). Ra controls the rising portion of the triangle and sine-wave and the “Low” state of the square wave. The magnitude of the triangle waveform is set at 1/3 Vcc: therefore, the durin of the ring portion of he rangle CxV_Cx/3xVocxRa | Shane pie WeevCe™ Tt” The duration of the falling portion of the triangle and the sine- wave, and the “High” state of the square-wave is: Raxc aha a CRY 5021/3 Ve9_. 5S, BARRO. 2°"T “7 -Vvec_! Voc 3*2Ra-Re Rp 3* Ra Thus a 50% duty cycle is achieved when Ra = RB. If the duty-cycle is to be varied over a small range about 50% only, the connection shown in Figure 2b is slightly more con- venient. If no adjustment of the duty cycle is desired, terminals 4 and 5 can be shorted together, as shown in Figure 2c, This connection, however, carries an inherently larger variation of the duty-cycle. With two separate timing resistors, the frequency is given by 1 PM TB Sac( RB 3 ac((+ey a) of if Ra =Rp=R £=0.3/RC (for Figure 2a) If a single timing resistor is used (Figures 2b and ), the fre- quency is F=0.15/RC even though none of the voltages are regulated inside the inte- grated circuit, This is due to the fact that both currents and thresholds are direct, linear function of the supply voltage and thus thei effects cancel. q Figure 2. Possible Connections forthe External Timing Resistors. 32DISTORTION ADJUSTMENT To minimize sine-wave distortion the 81 9 resistor between pins 11 and 12 is best made a variable one. With this arrange: ment distortion of less than 1% is achievable. To reduce this even further, two potentiometers can be connected as shown in Figure 3, This configuration allows a reduction of sine-wave distortion close to 0.5%. Figure 3. Connection to Achieve Minimum Sine-Wave stortion. ‘SELECTING TIMING COMPONENTS For any given output frequency, there is a wide range of RC ‘combinations that will work. However certain constraints are placed upon the magnitude of the charging current for opti- ‘mum performance. At the low end, currents of less than 0.1 HA are undesirable because circuit leakages will contribute sig nificant errors at high temperatures. At higher currents (1 >5 ‘mA), transistor betas and saturation voltages will contribute increasingly larger errors. Optimum performance will be ob- tained for charging currents of 1 u to I mA. If pins 7 and 8 are shorted together the magnitude of the charging current due to Ra can be calculated from RixVcc 1 _Vec (Ri # Ra) * Ry 5Rq A similar calculation holds for Rp. SINGLE-SUPPLY AND SPLIT-SUPPLY OPERATION’ The waveform generator can be operated either from a single power-supply (10 to 30 Volts) or a dual power-supply (#5 to 415 Volts). With a single power-supply the average levels of the triangle and sineowave are at exactly one-half of the supply voltage, while the square-wave alternates between +Vcc and ground. A split power supply has the advantage that all wave- forms move symmetrically about ground. ‘The square-wave output is not committed. A load resistor can ‘be connected toa different power-supply, as long as the applied voltage remains within the breakdown capability of the wave- form generator (30V). In this way, the square-wave output will be TTL compatible (load resistor connected to +5 Volts) while the waveform generator itself is powered from a higher supply voltage. FREQUENCY MODULATION AND SWEEP ‘The frequency of the waveform generator is a direct function of the DC voltage at terminal 8 (measured from +Vcc). By altering this voltage, frequency modulation is performed. For small deviations (eg. +10%) the modulating signal can be applied directly to pin 8 by merely providing ac coupling with «capacitor, as shown in Figure 4a. An external resistor between pins 7 and 8 is not necessary, but it can be used to increase input impedance. Without it (ie. terminals 7 and 8 connected together), the input impedance is 8k; with it, this impedance increases to (R + 8k). For larger FM. deviations or for frequency sweeping, the modulating signal is applied between the positive supply voltage and pin 8 (Figure 4b). In this way the entire bias for the current sources is created by the modulating signal and a very large (¢.g., 1000:1) sweep range is obtained (f= 0 at Veweep ~ 0)- Care must be taken, however, to regulate the supply voltage; in this configuration the charge current is no longer a function of the supply voltage (yet the trigger thresh- olds still are) and thus the frequency becomes dependent on the supply voltage. The potential on Pin 8 may be swept from Voc to 2/3 Vee +2V. Figure 4, Connections for Frequency Modulation (a) and Sweep (b)Application Note AN-01 Stable FSK Modems Featuring the XR-2207, XR-2206 and XR-2211 ( INTRODUCTION Frequency shift keying (FSK) is the most commonly-used method for transmitting digital data over telecommunications links. In order touse FSK,amodulator-demodulator (modem) isneeded to translate digital ’s and 0's into their respective frequencies and back again. This Applications Note describes the design of a modem using state-of-the-art Exar devices specifically intended for modem application. The devices featured in this Application Note are the XR-2206 and XR-2207 FSK modulators, and the XR-2211 FSK demodulator with carrier-detect capability. Because of the superior frequency stability (typically 20 ppm/°C) of these devices, a properly designed modem using them will be virtually free of the temperature and voltage-dependent drift problems associated with many other designs. In addition, the demodulator performance is independent of incoming signal strength variation over « 60 dB dynamic range. Because bias voltages are generated internally, the external parts count is much lower than in most other designs. The modem designs shown in this Applications Note can be used with mark and space frequencies anywhere from several Hertz to 100 kiloHertz THE XR-2206 FSK MODULATOR FEATURES © Typically 20 ppm/°C temperature stability © Choice of 0.5% THD sinewave, triangle, or squarewave output ‘© Phase-continuous FSK output ‘© Inputs are TTL and C/MOS compatible © Low power supply sensitivity (0.01%/V) © Split or single supply operation © Low external parts count OPERATION ‘The XR-2206 is deal for FSK applications requiring the spectral purity of a sinusoidal output waveform. It offers TTL and CJMOS compatibility, excellent frequency stability, and ease of application. The XR-2206 can typically provide a 3 volt pp sinewave output, Total harmonic distortion can be trimmed to 0.5%. If left untrimmed, itis approximately 2.5%. The circuit connection for the XR-2206 FSK Generator is shown in Figure 1. The data input is applied to pin 9. A high level signal selects the frequency (1/RgC3) Hz; a low level signal selects the frequency (1/RyC) Hz, (resistorsin ohms and capacitors in farads). For optimum stability, Re and Ry should bbe within the range of 10 k®2 to 100 k&. The voltage applied to pin 9 should be selected to fall between ground and V+. Note: Over and under voltage may damage the device, Potentiometers Ry and Ry should be adjusted for minimum total harmonic distortion. In applications where minimal dis- tortion is unnecessary, pins 15 and 16 may be left open- ( circuited and Rg may be replaced by a fixed 2000 resistor. In applications where a triangular output waveform is satisfactory, pins 13 thru 16 may be left open-circuited The output impedance at pin 2 is about 6002 with AC cou- pling normaly be used. aK a p= faeces Figure 1. The XR-2206 Sinusoidal FSK GeneratorTHE XR-2207 FSK MODULATOR FEATURES © Typically 20 ppm/°C temperature stability 4 Phase-continuous FSK output ‘© Provides both triangle and squarewave outputs ‘© Operates single-channel or two-channel multiplex ‘¢ Inputs are TTL and C/MOS compatible ‘© Split or single power supply operation ‘© Low power supply sensitivity (0.15%/V) ‘© Low external parts count OPERATION The XR-2207 isa stable FSK generator which is designed for those applications where only a triangle or squarewave output is required. It is capable of either single-channel or two-channel ‘multiplex operation, and can be used easly with either split or single power supplies. Figure 2 shows the XR-2207 using a single-supply and Figure 3 shows splitsupply operation. When used as an FSK modulator pins 8 and 9 provide the digital inputs. When the 2207 is used with a splitsupply, the threshold at these pins is approximately 42 volts, which isa level that is compatible with both TTL and C/MOS logic forms. When used with a single supply, the thresh- ld isnear mid-supply and is C/MOS compatible. Table 1 shows how to select the timing resistors Ry thru Ry to determine the output frequency based upon the logic levels applied to pins 8 and 9. For optimum stability, the values of R, and R3 should be selected to fall between 10 k®2 and 100 k& With pin 8 grounded, pin 9 serves as the data input. A high evel signal applied to pin 8 will disable the oscillator, When used inthis manner, pin 8 of the XR-2207 serves as the channel select input. For two-channel multiplex operation, pins 4 and 5 should be connected asshown by the dotted lines. (For single channel operation, pins 4 and 5 should be left open-circuited.) ‘The XR-2207 provides two outputs; a squarewave at.pin 13 and a trianglewave at pin 14, When used with a splitsupply, the trianglewave peak-to-peak amplitude is equal to V- and the de level is near ground. Direct coupling is usually used ‘With a single supply, the peak-to-peak amplitude is approxi- rately equal to 4V+, the DC level is at approximately mid- supply and AC coupling is usually necessery. In either case, the output impedance is typically 102 and is internally protected ‘against short circuits. ‘The squarewave output has an NPN open-collector configura- tion. When connected as shown in Figure 2 or 3 this output voltage will swing between V+ and the voltage at pin 12. ‘Note: For safe operation, current into pin 13 should be limited 10 20 mA, 38 Figure 3. The XR-2207 FSK Modulator Split Supply Operation, TABLE 1 XR.2207 FSK Input Control Logie Units: Resistors — Ohms; Capacitors — Fee THE XR-2211 FSK DEMODULATOR WITH CARRIER DETECT FEATURES © Typically 20 ppm/*°C temperature stabi © Simultaneous FSK and carrier detect output © Outputs are TTL and C/MOS compatible (© Wide dynamic range (2 mV to 3 ems) ‘© Split or single supply operation © Low power supply sensitivity (0.05%/V) ©“ Low external parts count OPERATION ‘The XR-2211 is a FSK demodulator which operates on the phase-lockedoop principle. Its performance is virtually independent of input signal strength variations over the range of 2 mV to 3 Vims. Figure 4 shows the circuit connection for the XR-2211. The center frequency is determined by fy = (1/C,R,) Hz, where capacitance is in farads and resistance is in ohms. Fy should be calculated to fall midway between the mark and space fre: quencies. ‘The tracking range (tA) is the range of frequencies over which the phase-locked loop can retain lock with a swept input signal. This range is determined by the formula: Af = (Rafo/Rs) Hz. ‘Af should be made equal to, or slightly less than, the difference between the mark and space frequencies. For optimum stability, choose an Rg between 10 KS and 100 k2. ‘The capture range (4Af,) is the range of frequencies over which the phase-locked loop can acquire lock. Its always less than the tracking range. The capture range is limited by C>, which, in conjunction with Rs, forms the loop filter time constant. In most modem applications, Af, = (80% - 99%) Af. ‘The loop damping factor (f) determines the amount of over- shoot, undershoot, or ringing presentin the phase-locked loop's, response to a step change in frequency. It is determined by $= Ye/GjIG,. For most modem applications, choose § = 4. ‘The FSK output filter time constant (rp) removes chatter from the FSK output. The formula is: 7p = RpCp. Normally calculate rp to be approximately equal to [0.3/(baud rate)] seconds, ‘The lock-detect filter capacitor (Cp) removes chatter from the , lock-detect output. With Rp = 510k, the minimum value of Cp can be determined by: Cp (uf) * 16/capture range in Hz. Note: Excessive values of Cp will unnecessarily slow the lock- detect response time. The XR-2211 has three NPN open collector outputs, each of which is capable of sinking up to 5 mA. Pin 7 is the FSK data ‘output, Pin 5 is the Qlock-detect output, which goes low when a carrier is detected, and Pin 6 is the Q lock detect output, which goes high when lock is detected. If pins 6 and 7 are ‘wired together, the output signal from these terminals will provide data when FSK is applied and will be “low” when no carrier is present. If the lock-detect feature is not required, pins 3, 5 and 6 may be left open-circuited. Figure 4, The XR-2211 FSK Demodulator with Carrier Detect DESIGNING THE MODEM Table 2 shows recommended component values for the three most commonly used FSK bands. In many instances, system constraints dictate the use of some non-standard FSK band. ‘The XR-2206/XR-2207, XR-2211 combination is suitable for any range of frequencies from several Hertz to 100 kiloHertz. Here are several guidelines to use when calculating non-standard frequencies: © For maximum baud rate, choose the highest upper fre- quency that is consistent with the system bandwidth. © The lower frequency must be at least 55% of the upper frequency. (Less than a 2:1 ratio) © For minimum demodulated output pulsewidth jitter, select an FSK band whose mark and space frequencies areboth high compared to the baud rate. (ie., for a 300 baud channel, mark and space frequencies of 2025 Hz and 2225 Hz would result in significantly less pulsewidth jitter For narrower spacing, the minimum ratio should be about 67%. than 300 Hz and 550 Hz). ‘© The values shown in Table 2 may be scaled proportionately * 3 : for mark and space frequencies, maximum baud rate, and © For any given pair of mark and space frequencies. there is, eh ay espe HF puha a ttl apprex a limit to the baud rate that can be achieved. When maxi- Dae) RE heels eliea owe. ‘mum spacing between the mark and space frequencies is used (Where the ratio is close to 2:1) the relationship mark-space frequency difference (Hz) 55, “~taximum data rate (baud) should be observed. TABLE 2 Recommended Component Values for Typical FSK Bands FSK Band XR-2207 XR-2206 XR2211 Si Baud Ria] Ris | Raa | 8: fy | fy [Ria] Rup] Roa | Ras | Raa | Rp | C. Rs|c, | G | cp | ep Pe fe | ft [EA] ee | ct ae | Co |Roa | Ros | Rra | Rea] C3 ]Ran | Ren Rs | Cr 300 | 1070| 1270 10 | 20 | 100] 100] .039 | 10 | 18 | 10 | 20 | 039] 10 | 18 | 100] 039] 01 00s] os 300 | 2025] 2225] 10 | 18 | 150| 160] 022] 10 | 16 | 10 | 18 | 022] 10 | 18 | 200].022].0047} .005 J .os 1200 | 1200} 2200} 20 | 30 | 20] 36|.022} 10 | 16 | 20 | 30 | 022] 10 | 18 | 30}.027| .01| 0022] .01 Units: Frequency — Hz; Resistors — kt; Capacitors — nF DESIGN EXAMPLES ‘A. Design a modem to handle a 10 kilobaud data rate, using the minimum necessary bandwidth. 1, Frequency Calculation Because we want to use the minimum possible band- width (lowest possible upper frequency) we will use a 55:100 frequency ratio. The frequency difference, or 45% of the upper frequency, will be 83% of 10,000. We therefore choose an upper frequency’ 83x 10,000 _ as 7 S444 Kia ~ 18.5 kHz, and the lower frequency: 0.55 x 18.5 kHz = 10.175 kHz ‘Component Selection For the XR-2207 FSK modulator, set Ry ~30k9. Now, select a value of Co to generate 10.175 kHz. with Ry: 10.175 kHz To choose Ry: 18.500 kHz — 10.175 kHz = 8.325 kHe = WCpR sR = 36K2. 1/(Co x 30,000) ; Co = 3300 pF. A good choice would be to use 10 k®? potentiom- eters for Ry, and Ro,, and to set Ryp = 24k2 and Rog = 30k. 7 b. For the XR-2206, we can make Ry equal to Ry and C3 equal to Cy above. To determine Rg 18.5 kHz = 1/RgC3 :Rg = 160. Use a 10kS potentiometer for Req and set Rep = 13 ko. For the XR-2211 demodulator, we need to first determine Ry and C,. First; fy = (fy, + fy)/2 = (10.175 + 18.500)/2 = 14.338 kHz. if we make Rg = 25k then 1/(C; x 25,000) = 14,338; C, = 2790 pF ~ 2700 pF. With that value of Cy, the precise value of Ry is now 25.8 k®. Select Rag = 18 kA and use a 10 k9 for Ryy. 3. Frequency Component Selection a. To calculate Ry, we first need our Af, which is 18,500 ~ 10.175, or 8.325 kHz. 8325 = (25,800 x 14,338)/Rs Rs = 44.4 k= 47 KO. % VGjICp. Then, To determine C2 use C_.= %4 Cy ;Cp = 670 pF. To select Cp, we use tp = [0.3/(baud rate)] seconds ‘7p = 0.3/10,000 = 30 psec. ; with Rg = 100k, Cp = 300 pF.oe 4, Lock Range Selection To select Cp, let us start with the actual lock range: AL= Rgfg/Rs Hz = 7870 Hz. If we assume a capture range of 80%, Afc = 6296 Hz; therefore, our total capture range or 48f¢ is 12,592 He. Our minimum value for Cp is (16/12,592) pf or 0.0013 uf. 5. Completed Circuit Example See Figure 5. B. Design a 3 kilobaud modem to operate with low output jitter. The bandwidth available is 13 kHz For this modem, we can take the values from 2 for the 300 baud modem operating at 1070 Hz and 1270 Hz, multiply our baud rate and mark and space frequencies by 10, and divide all capacitor values on the table by 10. Resistor values should be left as they are C. Design a 2 channel multiplex FSK modulator to operate at the following pairs of mark and space frequencies: 600 Hz and 900 Hz, and 1400 and 1700 Hz. (Each of these channels could handle about 400 beud.) For this task, we will use the XR-2207. The only real consideration here is that, if possible, we want to keep the following: resistances all between 10k and 100 k9: R,, Ry/Rp, Ry and Ra/Ry. The ratio between the maxi- mum and minimum frequencies is less than 3:1, so we should have no trouble meeting this criterion. If we set ‘our maximum frequency with an R of about 20 k®, we have: 1700 = 1/(Co x 20,000); Co = 0.029 pf which is approximately equal to 0.033 uf. Calculating Ry using 600 Hz and 0.033 uf, we get Ry = 50.5 k@. We can use Ryp = 47K and Ry, = 10KO. For Rp, we get 101 KS. Use Ryp = 91 KS and Raq = 20k. To determine R3, use: 1400 Hz = 1/R3Co, which gives us R, =21.6 KO. Use Rap = 18 k®2 and Ryq = 5 k2. Ry must generate a 300 Hz shift in frequency, the same as Rp. Therefore set Ry equal to Rp. Figure 5. Full Duplex FSK Modem Using XR-2206 and XR-221 1. (See Table 2 for Component Values.) ADJUSTMENT PROCEDURE ‘The only adjustments that are required with any of the circuits in this application note are those for frequency fine tuning. Although these adjustments are fairly simple and straight: forward, there are a couple of recommendations that should be followed, The XR-2207: Always adjust the lower frequency first with Ryp oF Rjy and a low level on pin 9. Then with a high level on pin 9, adjust the high fre: quency using Rog or Rag. The second adjust. ment affects only the high frequency, whereas the first adjustment affects both the low and the high frequencies. ‘The XR-2206: The upper and lower frequency adjustments are independent so the sequence is not impor- tant, ‘The XR-2211: With the input open-citcuited, the loop phase detector output voltage is essentially undefined 38 ‘and VCO frequency may be anywhere within the lock range. There are several ways that fo can be monitored: 1. Short pin 2 to pin 10 and measure fy at pin 3 with Cp disconnected; 2. Open Rs and monitor pin 13 or 14 with @ high-impedance probe; or 3. Remove the resistor between pins 7 and 8 and find the input frequency at which the FSK output changes state. Note: Do NOT adjust the center frequency of the XR-2211 by monitoring the timing capaci tor frequency with everything connected and Sees ( For further information regarding the use of the XR-2207, XR-2206 and XR-2211 refer to the individual product data sheets.Application Note AN-06 , Precision PLL System Using the XR-2207 and the XR-2208 INTRODUCTION The phase locked loop (PLL) isa versatile system block, suitable for a wide range of applications in data communications and signal conditioning. In most of these applications, the PLL is required to have a highly stable and predictable center frequency and a well. controlled bandwidth. Presently available monolithic PLL circuits often lack the frequency stability and the versatility required in these applications. This application note describes the design and the application of two-chip PLL system using the XR-2207 and the XR-2208 mono. lithic circuits. The XR-2207 is a precision voltage controlled oscillator (VCO) circuit with excellent temperature stability (+20 ppm/°C, typical) and linear sweep capability. The XR-2208 is an operational multiplier which combines a four quadrant multiplier and a high gain operational amplifier in the same package. Both circuits are designed to interface directly with each other with a minimum number of external components. Their combination functions as a high performance PLL, with the XR-2207 forming the VCO section of the loop, and the XR-2208 serving as the phase-detector and loop amplifier. As compared with the presently avalable single-chip PLL circuits such as the XR-210 or the Haris HI-2820, the two-chip PLL sys- tem described in this paper offersapproximately a factor of 10 improvement in temperature stability and center frequeney accuracy The system can operate from 0,01 Hz to 100 kHz, and its performance characteristics can be tilored to given design requirements with the choice of only four external components. 9 DEFINITIONS OF PLL PARAMETERS ‘The phase-locked loop (PLL) isa unique and versatile feedback. system that provides frequency selective tuning and filtering stow without the need for coils or inductors. It consists of three basic functional blocks: phase comparator, low-pass filter, and voltage-controlled oscillator, interconnected as shown in Figure 1, With no input signal applied to the system, the error voltage, Vg, is equal to zero. The VCO operates at a set “free-running” frequency, fy. If an input signal is applied to the system, the phase comparator compares the phase and frequency of the input signal with the VCO frequency and generates an error voltage, Ve(t), that is related to the phase and frequency dif ference between the two signals. This error voltage is then filtered and applied to the control terminal of the VCO. If bt the input signal frequency, f, is sufficiently close to fy, feed- se back causes the VCO to synchronize or “lock” with, the in Pe be coming signal. Once in lock, the VCO frequency is identical to the input signal, except fora finite phase difference we Figure 1. Block Diagram of a Phase-Locked Loop. Two key patameters of a phase-locked loop system are its “Jock” and “capture” ranges, These can be defined as follows: eesti cha Lock Range = The band of frequencies in the vicinity of f LAE Ec lagtiainl over which the PLL can maineain lock with an input signal It is also known as the “tracking” or “holding” range. Lock range increases as the overall loop gain of the PLL is increased. Pe rig! =i ua fissea ti oly ote Bee peeks orc anmee Clacteet gn aang eo cerctue-estaiae agesYortionale Figure 3. Circuit Interconnections for the Precision PLL System Using the XR-2207 and the XR-2208 Monolithic Circuits. (Splitsupply operation, #6 to x13V) Zi crc cance “Ts = grey caper = vienve2 ~ Figure 4, Circuit Interconncetions for Single Supply Operation. TABLE | Phase-Locked Loop Design Equations* 1 rie’ (1) Center Frequency: fo = gig, He (1) Loop Damping: = 37g = (2) Lock Range: (Af, Ifo (.9KRo/Rs) (8) Capture Range: (3) Phase Detector Gain: Ky = 0.5 Veg volts/radian Sea Where Vx. = Vt for split supply; Vee = V*/2 for single (abt) = 2 J@ supply. : h ») Overdamped Loop (> 1) (4) VCO Conversion Gain: Ky = ste ad/se/volt ee (Affe) = 0.8(Ro/R) yaoi boning ease! (6) Low Pas Filter Time Constant: += S11 sec. **See Figures 3 and 4 for component designationThe PLL responds only to those input signals sufficiently close to the VCO frequency, fo to fall within the “lock” or “capture” ranges of the system. Iis performance characteristics, there- fore, offer a high degree of frequency selectivity, with the selectivity characteristics centered about fo. Figure 2 shows the typical frequency-towoltage transfer characteristics of the PLL, The input is assumed to be a sine wave whose frequency is swept slowly, over a broad frequency range covering both the “lock” and the “capture” ranges of the PLL. The vertical scale corresponds to the filtered loop error voltage, V, appear ing at the VCO control terminal. As the input frequency, f, is swept up (Figure 2(a)) the sys- tem does not respond to the input signal until the input frequency reaches the lower end of capture range, fo, Then, the loop suddenly locks on the input signal, causing a positive jump in the error voltage Vj. Next, Vg varies at a slope equal to the reciprocal of VCO voltage-to-frequency conversion gain, {K), and goes through zero at & = fy. The loop tracks the in- put frequency until {, reaches the upper edge of the lock range, fy. Then the PLL loses lock, and the error voltage drops to zero. If the input frequency is swept back slowly, from high towards low frequencies the cycle repeats itself, with the characteristics shown in Figure 2(b). The loop cap- tures the signal at the upper edge of the capture range, fo}, and tracks it down the lower edge of the lock range, fy. With reference to the figure, the “lock” and the “capture” ranges can be defined as Lock Range = Af, = fy — fir fe = fou — Capture Range The gain parameters associated with the PLL are defined as follows: Phase Detector Gain, K#: Phase detector output per unit of phase-difference between the two signals appearing at the phase detector inputs. It is normally measured in volts per ra~ dian, VCO Conversion Gain, Ky: VCO frequency change per unit of input voltage. It is normally measured in radians/sec./volt. Loop Gain, K,: Total d, gain around the feedback loop. It is equal to the product of K9 and K,. Loop Damping Factor, {: Defines the response of the loop error voltage Vq, to a step change in frequency. If § <1, the loop is underdamped; and the error voltage Vg will exhibit an underdamped response for a step change of signal frequency. The lock range of the phase-locked loop is controlled by the loop gain, Ky. The capture range and the damping factor are controlled by both the loop gain and the low pass filter. PRECISION PLL USING XR-2207 AND XR-2208 The XR-2207 VCO and the XR-2208 operational multiplier can be interconnected as shown in Figure 3, to form a highly stable PLL system. The circuit of Figure 3 operates with sup- ply voltages in the range of 46 volts to £13 volts; and over a frequency range of 0.01 Hz to 100 kHz. In the PLL system of Figure 3, all the basic performance characteristics of the PLL ‘ean be controlled and adjusted by the choice external 4 com- ponents identified as resistors Ro and Rx, and the capacitors, Co and Cy, Cp and Ro control the VCO center frequency; Ri and C, determine the tracking range and the low pass filter characteristics. The two-chip PLL system can be readily con- verted to single supply operation by inter-connecting the cit- cuit as shown in Figure 4. ThePLL circuit of Figure 4 operates over a supply voltage range of +12V to +26V. For best results, the timing resistor Ro should be in the range of 5k to 100k, and Ry > Ro. Under these conditions, the basic parameters of the PLL can be easily calculated from the de- sign equations listed in Table 1. Design Example ‘As an example, consider the design of a PLL system using the circuit of Figure 3, to meet the following nominal performance specifications: a) Center Frequency = 10 kHz ') Tracking Range = 20% (© kHz to 11 kH2) 6) Capture Range = 10% (9.5 kHz to 10.5 kHz) Solution: 4) Set Center Frequency: Choose Ro = 10k (Arbitrary choice for Sk < Ro < 100k) Then, from equation 1 of Table 1 Co =(I/foRo) = 0.01 uF b) Set Lock Range: From equation 2 of Table 1: R, = (045) Ry = 45k «) Set Capture Range Since capture range is significantly smaller than Lock range, equation 8() applies. Solving equation 8(a) for Cy , one obtains Cy = 0.032 uF aApplication Note AN-14 A High Quality Function Generator System ® Using the XR-2206 INTRODUCTION Waveform or function generators capable of producing AM/FM modulated sine wave outputs find a wide range of applications in lectrical measurement and laboratory instrumentation. This application note describes the design, construction and the perform. ance of such a complete function generator system suitable for laboratory usage or hobbyist applications. The entire function generator is comprised of single XR-2206 monolithic IC and a limited number of passive circuit components. It provides the engineer, student, or hobbyist with highly versatile laboratory instrument for waveform generation at a very small fraction of the cost of conventional function generators available today. GENERAL DESCRIPTION ‘The basic circuit configuration and the external components necessary for the high-quality function generator system is shown in Figure 1, The circuit shown in the figure is designed to operate with either a 12V single power supply, or with a 26V split supplies. For most applications, splitsupply opera tion is preferred Since it results in an output DC level which is nearly at ground potential. ‘The circuit configuration of Figure 1 provides three basic waveforms: sine, triangle and square wave, There are four overlapping frequency ranges which give an overall frequency range of | Hz to 100 kHz. In each range, the frequency may be varied over a 100:1 tuning range. ‘The sine or triangle output can be varied from 0 to over 6V (peak to peak) from 2 600 ohm source at the output terminal A squarewave output is available at the syne output terminal for oscilloscope synchronizing or driving logic circuits. TYPICAL PERFORMANCE CHARACTERISTICS ‘The performance characteristics listed below are not guar- anteed or warranted by Exar. However, they represent the typical performance characteristics measured by Exar’s appli- cation engineers during the laboratory evaluation of the function generator system shown in Figure 1. The typical performance specifications listed below apply only when all of the recommended assembly instructions and adjustment pro: cedures are followed (a) Frequency Ranges: The function generator system is designed to operate over four overlapping frequency ranges: 1 Hz to 100 Hz 10 Hz to 1 kHz 100 He to 10 kHz 1 kHz to 100 kHz ‘The range selection is made by switching in different tim- ing capacitors. 42 (b) Frequency Setting: At any range setting, frequency can be varied over a 100:1 tuning range with a potentiometer (see Ry3 of Figure 1). (©) Frequency Accuracy: Frequency accuracy of the XR- 6 is set by the timing resistor R and the timing capac. itor C, and is given as f= 1/RC The above expression is accurate to within £5% at any range setting. The timing resistor R is the series combina- tion of resistors Rq and Rj3 of Figure 1. The timing ‘capacitor C is any one of the capacitors C3 through Cg, shown in the figure (@) Sine and Triangle Output: The sine and triangle output amplitudes are variable from OV to 6 Vpp. The amplitude is set by an external potentiometer, Rj of Figure 1. At any given amplitude setting, the triangle output ampli- tude is approximately twice as high as the sinewave out- put. The internal impedance of the output is 60002. (©) Sinewave Distortion: The total harmonic distortion of sinewave is less than 1% from 10 Hz to 10 KFiz and less than 3% over the entire frequency range. The selection of a waveform is made by the triangle/sine selector switeh, So (© Syne Output: The syne output provides a 50% duty cycle pulse output with either full swing or upper half swing of the supply voltage depending on the choice of sync out- put terminals on the printed eircuit board (see Figure 1). (@) Frequency Modulation (External Sweep): Frequency can bbe modulated or swept by applying an external control voltage to sweep terminal (Terminal I of Figure 1). When not used, this terminal should be left open-ircuited. The ‘open circuit voltage at this terminal is approximately 3V above the negative supply voltage and its impedance is approximately 1000 ohms,‘AMPLITUDE NOTE: i I I a. 2 ai ‘SYNC OUTPUT (FULL SWING) (HALE swinc) FREQUENCY 1. For single supply operation lift GND conneetion ke 2. For maximum output, Rx may be open. Ry = 68 KA is recommended for external amplitude modulation, ing R12 across torminals Rand B intact, and eonneect terminal A to GND. Figure 1, Circuit Connection Diagram for Function Generator. (See Note | for single supply operation.) (i) Amplitude Modulation (AM): The output amplitude varies linearly with modulation voltage applied to AM input (terminal Q of Figure 1). The output amplitude reaches its minimum as the AM control voltage approaches ‘the half of the total power supply voltage. The phase of the output signal reverses as the amplitude goes through its minimum value. The total dynamic range is approxi- mately $5 4B, with AM control voltage range of 4V referenced to the half of the total supply voltage. When not used, AM terminal should be left open circuited. ( Power Source: Split supplies: 26V, or single supply: +12V. Supply Current: 15 mA (See Figure 3). EXPLANATION OF CIRCUIT CONTROLS: Switches Range Select Switch, S1: Selects the frequency range of opera- tion for the function generator. The frequency is inversely proportional to the timing capacitor connected across Pins 5 and 6 of the XR-2206 cireuit. Nominal capacitance values and frequency ranges corresponding to switch positions of SI are as follows: Position Nominal Range Timing Capacitance 1 1 Hz to 100 Hz 1 uF 2 10 Hz to 1 kHz 0.1 uF 3 100 Hz to 10 kHz 0.01 uF 4 1 kHz to 100 kHz 0.001 uF If additional frequency ranges are needed, they can be added by introducing additional switch positions, Triangle(Sine Waveform Switch, $2: Selects the triangle or sine ‘output waveform. ‘Trimmers and Potentiometers DC Offset Adjustment, R9: The potentiometer used for ad Justing the DC offset level of the triangle or sine output wave- form. Sinewave Distortion Adjustment, R10: Adjusted to minimize the harmonic content of sinewave output. Sinewave Symmetry Adjustment, R11: Adjusted to optimize the symmetry of the sinewave output. Amplitude Control, R12: Sets the amplitude of the triangle or sinewave output.Frequency Adjust, R13: Sets the oscillator frequency for any range setting of S1. Thus, R13 serves as a frequency dial on a conventional waveform generator and varies the frequency of the oscillator over an approximate 100 to 1 range. Terminals A. Negative Supply ~6V B, Ground C. Positive Supply +6V D. Range 1, timing capacitor terminal E, Range 2, timing capacitor terminal F, Range 3, timing capacitor terminal G. Range 4, timing capacitor terminal H. Timing capacitor common terminal 1. Sweep Input J, Frequency adjust potentiometer terminal K. Frequency adjust potentiometer negative terminal L. Syne output (1/2 swing) M.Syne output (full swing) N. Triangle/sine waveform switch terminals . Triangle/sine waveform switch terminals P. Triangle or sinewave output Q.AM input R. Amplitude control terminal supply PARTS LIST The following is list of extemal circuit components necessary to provide the circuit interconnections shown in Figure 1. Capacitors: €1,C2,C7 Electrolytic, 10 uF, 10V rc Mylar, uF, nonpolar, 10% C4 Mylar, 0.1 uF, 10% cs Mylar, 0.01 nb, 10% cé Mylar, 1000 pF, 10% Resistors RI 30 KO, 1/4W, 10% R2 100 K92, 1/4W, 10% R3,R7 1 KQ, 1/4W, 10% R4 9 KQ, 1/4W, 10% RS, R6 5 KQ, 1/4W, 10% R8 3002, 1/4W, 10% RX 62 KM, 1/4 W, 10% (RX can be eliminated for maximum output) Potentiometers: RO Trim, 1 MQ, 1/4W RIO Trim, 1K, 1/4W Ri Trim, 25 KQ, 1/4W ‘The following additional items are recommended to convert the circuit of Figure 1 to a complete laboratory instrument: Potentiometers: R12 ‘Amplitude control, linear, SO KQ RIB Frequency control, audio taper, 1 M& Switches: si Rotary switch, I-pole, 4 pos. 82 Toggle or slide, SPST 44 Case 7° x4” x4” (approx.) Metal or Plastic (Gee Figures 4(a) and 4(b).) Power Supply: Dual supplies 6V or single +12V Batteries or power supply unit (See Figures 3(a) and 3(b).) Miscellaneous: Knobs, solder, wires, terminals, etc. BOARD LAYOUT Figures 2(a) and 2(b) show the resommended printedeircuit board layout for the function generator circuit of Figure 1. (a) Split Supply PC Board Layout (8) Single Supply PC Board Layout Figure 2. Recommended PC Board Layout for Function Generator Cireuit of Figure 1 RECOMMENDED ASSEMBLY PROCEDURE ‘The following instructions and recommendations for the as sembly of the function generator assume that the basic PC board layout of Figures 2(a) or 2(b) is used in the circuit assembly.Al the parts of the generator, withthe exception of frequency adjust potentiometer, amplitude control potentiometer, triange/sine switch and frequency range select switch, are mounted on the circuit board Install and solder all resistors, capacitors and trimmer resistors on the PC board first. Be sure to observe the polarity of capacitors C1, C2 and C7. The timing capacitors C3, C4, C5 and C6 must be non-polar type. Now install ICI on the board. We recommend the use of an IC socket to prevent possible damage to the IC during soldering and to provide for easy replacement in case of a malfunction. The entire generator board along with power supply or batter {es and several switches and potentiometers will fit into a case of the type readily available at electronic hobby shops. It will be necessary to obtain either output jacks or terminals for the ‘outputs and AM and frequency sweep inputs. Install the frequency adjust pot, the frequency range select switch, the output amplitude control pot, the power switch, andthe triangle/swine switch on the case, Next, install the PC board in the case, along with a power supply. Any simple power supply having reesonable regulation may be uted, Figure 3 gives some recommended power supply config. uration. aes feow (&) Battery Power Supply 5, D6: 1NA7365 oF similar 1,2! Electrolyte, 800 uF/12 VOC i, A2: 510, 1/20, 10% Figure 3. Recommended Power Supply Configurations. 45 Precaution: Keep the lead lengths small for the range selector switch. Figure 4 gives an example of the fully assembled version of the funetion generator system described above. Figure 4. Typical Example of a Fully Assembled Function Generator. ADJUSTMENT PROCEDURE When assembly is completed and you are ready to put the function generator into operation, make sure that the polarity of power supply and the orientation of the IC unit are correct. Then apply the DC power to the unit. To adjust for minimum distortion, connect the scope probe to the triangle/sine output. Close $2 and adjust the amplitude control to give non CHUSETTS. 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