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    The VLSI Design Flow

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    Sudhakar Sudha
    Specifications describe the functionality and architecture of a digital IC circuit to be designed. A behavioral description analyzes the design and is simulated to test functionality. An RTL description is created using HDLs and synthesized into a gate-level netlist of gates and connections meeting timing, power and area specifications. Finally, a physical layout is made and verified before fabrication.

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    The VLSI Design Flow

    Uploaded by

    Sudhakar Sudha
    15 views2 pages
    Specifications describe the functionality and architecture of a digital IC circuit to be designed. A behavioral description analyzes the design and is simulated to test functionality. An RTL description is created using HDLs and synthesized into a gate-level netlist of gates and connections meeting timing, power and area specifications. Finally, a physical layout is made and verified before fabrication.

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    Design Flow

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    Specifications describe the functionality and architecture of a digital IC circuit to be designed. A behavioral description analyzes the design and is simulated to test functionality. An RTL description is created using HDLs and synthesized into a gate-level netlist of gates and connections meeting timing, power and area specifications. Finally, a physical layout is made and verified before fabrication.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    15 views2 pages

    The VLSI Design Flow

    Uploaded by

    Sudhakar Sudha
    Specifications describe the functionality and architecture of a digital IC circuit to be designed. A behavioral description analyzes the design and is simulated to test functionality. An RTL description is created using HDLs and synthesized into a gate-level netlist of gates and connections meeting timing, power and area specifications. Finally, a physical layout is made and verified before fabrication.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    The VLSI Design Flow

    Specifications comes first, they describe abstractly the functionality, interface, and the
    architecture of the digital IC circuit to be designed.

    Behavioral description is then created to analyze the design in terms of functionality,


    performance, compliance to given standards, and other specifications.

    RTL description is done using HDLs. This RTL description is simulated to test
    functionality. From here onwards we need the help of EDA tools.

    RTL description is then converted to a gate-level netlist using logic synthesis tools. A
    gate-level netlist is a description of the circuit in terms of gates and connections between
    them, which are made in such a way that they meet the timing, power and area
    specifications.

    Finally a physical layout is made, which will be verified and then sent to fabrication.

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