A

Presentation
On
VLSI Design
( Front End & Back End )
Contents
 VLSI Design  Back End
 VLSI Design Flow  Synthesis
 Ideas  Synthesis Verification
 Specifications  Place & Route
 Design Architecture  Place & Route Steps
 RTL Coding  Parasitic Extraction
 HDL  Static Timing Analysis
 Difference Between VHDL &  Post Layout Verification
Verilog
 Application Of VLSI
 RTL Verification
 RTL Verification Wave Form
 Synthesis
 FPGA Kit
 Foundry
 IC Chip
 Front End
Introduction : VLSI Design

 A VLSI (Very Large Scale Integration) system integrates millions of “electronic

components” in a small area (few mm2  few cm2).
 design “efficient” VLSI systems that has:
 Circuit Speed ( high )
 Power consumption ( low )
 Design Area ( low )
VLSI : Design Flow
1. idea (need) 2. specifications 3. design 4. RTL coding
architecture

8.IC Chip 7.Foundry 5. RTL

6. Synthesis Verification
Ideas
Any thing we needs chip

• Microprocessor
• Microcontroller
• Memories
• Printer
• Mobile
• Digital security lock
 Specifications

 This is the crucial step as it will affect the future of the product. Here, vendors
may want to get feedback from potential customers on what they are looking
for
 Instruction set
 Interface (I/O pins)
 Organization of the system
 Functionality of each unit in the system, and how to communicate it to
other units.
Design architecture

 This is where the main work starts. With the help of the specification sheet the
target IC’s architecture is decided and a layout for same is created by design
engineers using EDA tools.

EDA Tools :
• Synopsys – astro
• Active hdl
• Xilinx - ise design suite
• Cadence - encounter digital ic design
RTL coding
 RTL - register transfer level.
 This implies that the VHDL/VERILOG code written based on the architecture
describes how data is transformed as it is passed from register to register.

RTL coding tools

 xilinx ise
 Vim
 Emacs
 conTEXT
 HDL TurboWriter
HDL – Hardware Description Language
ƒ A programming language that can describe the functionality and timing
of the hardware.

Types of HDL

 VHDL ( Very High Speed Integrated Circuit Hardware Description

Language )
 VERILOG
 System VERILOG
Difference Between VHDL & VERILOG

VHDL VERILOG
 Not case sensitive.  Case sensitive.
 Difficult to learn.  Easy to learn.
 Based on pascal & ada.  Based on c.
 Strongly typed.  Not strongly typed.
RTL Verification
 RTL simulation and verification is one of the important step. This ensures that
the design is logically correct and without major timing errors. It is
advantageous to perform this step, especially in the early stages of the design

RTL verification
xilinx ise
tools
 Modelism
 Verilog - XL
 Finism
 Test Builder
RTL verification wave form
Synthesis
 This is where the design now start to get physical. Logic synthesis is a process by
which the desired circuit behavior i.e. Register Transistor Level is turned into a
design in terms of logic gates which drives the circuit or architecture.

Synthesis tools/kit
 FPGA ( Altera, Digiland, Xilinx )
 CPLD ( Altera, Digiland )
FPGA KIT
Field programmable gate array (FPGA)
• It is a IC which can be be programmable by user to capture the logic.
• Capable to capturing 100,000 designed gates.
Foundry

The design is sent for Fabrication for mass production to foundry .

IC Chip
Front End
 The frontend flow is responsible to determine a solution for a given problem or
opportunity and transform it into a RTL circuit desc\ription.

Problem

Solution Specification

Behavioural Representation

RTL Coding (VHDL/Verilog)

Functional Verification

No Yes
Verification? Back End
Back End
 The backend process is responsible for the physical implementation of a circuit. It
transforms the RTL circuit description into a physical design, composed by gates
and its interconnections. The main phases of the backend process are Synthesis
and Place & Route.
A B
Synthesis
Static Timing Analysis
Synthesis Verification
No
Timing?
No
Verification? Yes

Yes Post-Layout Verification

Place & Route B
No
Verification?
Parasitic Extraction
Yes

A The End
Synthesis
 Synthesis is responsible for converting the RTL description into a structural gate
level based netlist. This netlist instantiates every element (standard cells and macros)
that compose the circuit and its connections.
 Synthesis can be described as follows:
Synthesis = Translation + Optimization + Mapping
 Synopsys Design Compiler is the tool used to perform a logical synthesis. Its inputs
are:
 The RTL description – Verilog or VHDL;
 The GTECH library – General technology library. Not tied to any specific
technology (gates, flip flops);
 Design Ware Library –Synthetic library (adders, multipliers, comparators, etc).
 The standard cell library – the specific target library;
 The defined constraints – synthesis goals regarding timing, area, capacitance,
max transition, fanout. Delivered by the Frontend team.
 Design Environment: The operating conditions (Libraries corners), wire load
models.
Synthesis Verification
 The first step is to verify a set of reports, which have information about timing,
area, fanout and shows the violations to the defined constraints.
 These reports must be interpreted to check if there are violations (setup time, hold
times, area, max transition, etc.).
 In case of violations DC can try to fix them by running optimization algorithms. If
DC cannot fix the violations, one must go back to RTL coding. With these reports it
is possible to check if the design is synthesizable and, therefore, if it is possible to
proceed.
 The final verification before proceeding to Place&Route is to run Formality, which is
a logical verification tool. It takes the final netlist generated by DC and checks the
logical equivalence with the RTL description.
Place & Route
 Place & Route is the backend stage that converts the gate level netlist produced
during synthesis into a physical design. Although the name denotes for two phases,
the Place & Route stage can be divided in three steps: Placement, Clock Tree
Synthesis (CTS) and Routing.
 Clock tree synthesis is the creation of a balanced buffer tree in all high fanout clock
nets to avoid violations regarding clock skew, max transition time, capacitance and
setup and hold times.
 Routing is done in three phases: Global Routing (design routing nets), Track
Assignment (assign nets to specific metal layers), and Search & Repair (fix
violations)
Placement CTS Routing

Empty miliway library Define Clock Congestion Map

Load netlist Load Clk Tree Syn. Sets Route Clk Nets

Connect cells pins Remove Auto Buffers Route Signal Nets

Load TLU+ files Compile Clk Tree Errors

Load floorplan Errors FILL & DCAP cells in gaps

Laod Design Cons. Set Not to Touch Attribs. Redundancy

Check Spl Design Cons. IR Drop Analysis Run DRC & LVS

Antenna Issues Static Timing Analysis Save Database

ICC Int. Sets Sign Off

Coarse Plcmnt

Legalize

Scan Chain

Optimize Spare Cells

Power & GND

Routing Guides
Parasitic Extraction
 Parasitic extraction has the objective to create an accurate RC model of the circuit
so that future simulations and timing, power and IR Drop analyses can emulate the
real circuit response.
 Only with this information, all the analyses and simulations can report results close
to the real functioning of the circuit. This way this stage needs to precede all
signoff analyses.
Static Timing Analysis
 STA is a method to obtain accurate timing information without the need to
simulate the circuit.
 It allows detecting setup and hold times violations, as well as skew and slow paths
that limit the operation frequency.
 Synopsys Prime Time allows running STA over a physical design, for each corner.
Taking as inputs the post-layout netlist and parasitic and standard cells information
it outputs a series of reports, which give the possibility to detect timing violations.
Post Layout Verification
 The huge number of transistors in a circuit can make the voltage level drop below a
defined margin that ensures that the circuit works properly.
 IR Drop analysis allows checking the power grid to ensure that it is strong enough
to hold that minimum voltage level.
 Synopsys Prime Rail is the tool that outputs IR-drop and EM analyses reports.
 The final step is to run Synopsys Hercules which is a DRC/LVS verification tool.
 DRC (Design Rules Checking) checks if the foundry geometric and connectivity
rules are met.
 Examples of DRC´s include: Metal to metal spacing; well to well spacing; minimum
metal width; Antenna Effect; Metal fill density.
 LVS (Layout Versus Schematic) checks if the physical circuit corresponds to the
original circuit schematic.
Application of VLSI